Apparatus and method for a core for implementing a communications port

1. An apparatus comprising a core for implementing a communications port, the core being operable to divide the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing, whereby each sub-port is allocated a corresponding data transfer capacity, wherein the core comprises:

a plurality of sequential logic elements operating at a plurality of data transfer rates corresponding to the data transfer capacities of the sub-ports, wherein the plurality of sequential logic elements are used to implement time division multiplexing by allowing data associated with each sub-port to be stored separately as the data is passed along a pipeline, wherein each sequential logic element is coupled to a corresponding control logic that is configured to distribute data to the sequential logic in a format which is suitable for the pipeline, and wherein only one of the plurality of sequential logic elements is active during any given phase of a phase cycle; and

combinatorial logic operating at the full data transfer capacity of the port which is divided among the plurality of sub-ports, wherein the combinatorial logic is shared in the core by the plurality of sub-ports, wherein the combinatorial logic is configured to receive data from one of the plurality of sequential logic elements associated with a sub-port during any given phase of a phase cycle, wherein the combinatorial logic remains active during all phases of the phase cycle, and wherein the combinatorial logic comprises a finite state machine for controlling the combinatorial logic to operate upon the data associated with each sub-port.

2. The apparatus of claim 1 , wherein the sequential logic comprises a plurality of registers, wherein each register corresponds to a sub-port.

3. The apparatus of claim 2 , wherein a capacity of a register is matched to the transfer capacity of a respective sub-port.

4. The apparatus of claim 2 , wherein at least one sub-port is supported by more than one register.

5. The apparatus of claim 2 comprising control logic operable to receive data at a rate corresponding to the data transfer capacity of the port and to load the received data into the registers in a format which is compatible with a pipeline of the core.

6. The apparatus of claim 1 , wherein the port is associated with a plurality of data lanes, and wherein the core is operable to divide the data transfer capacity of the port among the plurality of sub-ports by allocating one or more of the data lanes to each sub-port.

7. The apparatus of claim 1 , wherein at least one sub-port has a data transfer capacity which is larger or smaller than a data transfer capacity of at least one other sub-port.

8. The apparatus of claim 1 comprising a cyclic redundancy check (CRC) calculator.

9. The apparatus of claim 1 comprising a plurality of said cores.

10. The apparatus of claim 1 , wherein the communications port is configured to support PCI Express.

11. The apparatus of claim 1 , wherein the apparatus comprises an integrated circuit comprising the core for implementing the communications port.

12. The apparatus of claim 11 , wherein the integrated circuit is an application specific integrated circuit.

13. The apparatus of claim 1 , wherein the apparatus forms a switch.

14. A computer system comprising a core for implementing a communications port, the core being operable to divide the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing, whereby each sub-port is allocated a corresponding data transfer capacity, wherein the core comprises:

a plurality of sequential logic elements operating at a plurality of data transfer rates corresponding to the data transfer capacities of the sub-ports, wherein the plurality of sequential logic elements are used to implement time division multiplexing by allowing data associated with each sub-port to be stored separately as the data is passed along a pipeline, wherein each sequential logic element is coupled to a corresponding control logic that is configured to distribute data to the sequential logic in a format which is suitable for the pipeline, and wherein only one of the plurality of sequential logic elements is active during any given phase of a phase cycle; and

combinatorial logic operating at the full data transfer capacity of the port which is divided among the plurality of sub-ports, wherein the combinatorial logic is shared in the core by the plurality of sub-ports, wherein the combinatorial logic is configured to receive data from one of the plurality of sequential logic elements associated with a sub-port during any given phase of a phase cycle, wherein the combinatorial logic remains active during all phases of the phase cycle, and wherein the combinatorial logic comprises a finite state machine for controlling the combinatorial logic to operate upon the data associated with each sub-port.

15. A method for implementing a communications port, the method comprising a core dividing the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing, whereby each sub-port is allocated a corresponding data transfer capacity, wherein the core comprises:

a plurality of sequential logic elements operating at a plurality of data transfer rates corresponding to the data transfer capacities of the sub-ports, wherein the plurality of sequential logic elements are used to implement time division multiplexing by allowing data associated with each sub-port to be stored separately as the data is passed along a pipeline, wherein each sequential logic element is coupled to a corresponding control logic that is configured to distribute data to the sequential logic in a format which is suitable for the pipeline, and wherein only one of the plurality of sequential logic elements is active during any given phase of a phase cycle; and

combinatorial logic operating at the full data transfer capacity of the port which is divided among the plurality of sub-ports, wherein the combinatorial logic is shared in the core by the plurality of sub-ports, wherein the combinatorial logic is configured to receive data from one of the plurality of sequential logic elements associated with a sub-port during any given phase of a phase cycle, wherein the combinatorial logic remains active during all phases of the phase cycle, and wherein the combinatorial logic comprises a finite state machine for controlling the combinatorial logic to operate upon the data associated with each sub-port.