Method for production of chip-integrated antennae with an improved emission efficiency
View Patent ↗The method is to fabricate a microelectronic device with an integrated antenna. This method may include forming at least a first semiconducting layer on a substrate, forming in at least one zone of the first semiconducting layer of a structure to limit the circulation of current in the zone of the first semiconducting layer, forming a plurality of layers on the semiconducting layer and at least one antenna in the plurality of layers, with the antenna being formed opposite the zone. The antenna may be operable at radio frequencies above 10 GHz, and may have an improved emission efficiency.
1. A method for fabricating a microelectronic device including at least one integrated antenna, the method comprising:
forming a structure for limiting circulation of current in a zone of a semiconducting layer, the structure for limiting circulation of current comprising at least one reverse biased junction in the zone of the semiconducting layer on a substrate; and
forming a plurality of layers on the semiconducting layer including at least one antenna formed opposite the at least one reverse biased junction.
2. A method according to claim 1 wherein forming the structure for limiting circulation of current further comprises forming at least one insulating block in the zone of the semiconducting layer.
3. A method according to claim 1 wherein forming the structure for limiting circulation of current further comprises:
forming a mask on the semiconducting layer with at least one opening therein;
etching the semiconducting layer through the mask to form at least one opening in the semiconducting layer; and
filling the at least one opening in the semiconducting layer with a dielectric material.
4. A method according to claim 1 wherein forming the structure for limiting circulation of current comprises:
forming a mask on the semiconducting layer with at least one opening therein; and
doping the semiconducting layer through the mask to form the at least one reverse biased junction.
5. A method according to claim 4 wherein the semiconducting layer has a first type doping; and wherein doping through the semiconductor layer is a second type doping.
6. A method according to claim 1 wherein the semiconducting layer comprises at least one epitaxial layer.
7. A method according to claim 1 wherein the at least one antenna comprises a dipole including two conducting branches.
8. A method for fabricating a microelectronic device comprising:
forming a structure for limiting circulation of current in a zone of a semiconducting layer by forming at least one reverse biased junction in the zone of the semiconducting layer; and
forming at least one antenna opposite the at least one reverse biased junction.
9. A method according to claim 8 wherein forming the structure for limiting circulation of current further comprises forming at least one insulating block in the zone of the semiconducting layer.
10. A method according to claim 8 wherein forming the structure for limiting circulation of current further comprises:
forming a mask on the semiconducting layer with at least one opening therein;
etching the semiconducting layer through the mask to form at least one opening in the semiconducting layer; and
filling the at least one opening in the semiconducting layer with a dielectric material.
11. A method according to claim 8 wherein forming the structure for limiting circulation of current comprises:
forming a mask on the semiconducting layer with at least one opening therein; and
doping the semiconducting layer through the mask to form the at least one reverse biased junction.
12. A method according to claim 11 wherein the semiconducting layer has a first type doping; and wherein doping through the semiconductor layer is a second type doping.
13. A method according to claim 11 wherein the semiconducting layer comprises at least one epitaxial layer.
14. A method according to claim 11 wherein the at least one antenna layer comprises a dipole including two conducting branches.
15. A microelectronic device comprising:
a substrate;
at least one semiconducting layer adjacent said substrate;
a structure for limiting circulation of current in a zone of said at least one semiconducting layer;
said structure for limiting circulation of current comprising at least one reverse biased junction in the zone of said at least one semiconducting layer; and
a plurality of layers adjacent said at least one semiconducting layer including at least one antenna positioned opposite said at least one reverse biased junction.
16. A microelectronic device according to claim 15 wherein said structure for limiting circulation of current further comprises at least one insulating block in the zone of said at least one semiconducting layer.
17. A microelectronic device according to claim 15 wherein said at least one antenna comprises a dipole including two conducting branches.
18. A microelectronic device according to claim 15 wherein said at least one antenna is configured to operate at a frequency of at least about 10 GHz.
19. A microelectronic device according to claim 15 wherein said substrate has a resistivity of at least about 50 106 cm.
20. A microelectronic device comprising:
a substrate;
a semiconducting layer adjacent said substrate;
at least one reverse biased junction in a zone of said semiconducting layer; and
at least one antenna opposite the zone of said semiconducting layer.
21. A microelectronic device according to claim 20 wherein said at least one antenna comprises a dipole including two conducting branches.
22. A microelectronic device according to claim 20 wherein said at least one antenna is configured to operate at a frequency of at least about 10 GHz.
23. A microelectronic device according to claim 20 wherein said substrate has a resistivity of at least about 50 Ωcm.