High efficiency, high slew rate switching regulator/amplifier

1. A regulating apparatus having an output node and being operative for regulating the voltage at said output node with respect to a common node to a desired value set by a reference signal provided to said regulating apparatus, said regulating apparatus comprising:

a linear amplifier stage operative for receiving said reference signal and being capable of sourcing current to said output node when a present voltage level at said output node is less than a desired voltage level at said output node set by said reference signal; and

a switching circuit comprising a first semiconductor switch connected between a power supply and a first node, a diode whose cathode is connected to said first node and whose anode is connected to said common node, an inductor having one terminal connected to said first node and another terminal connected to said output node, a second semiconductor switch connected in parallel with said inductor;

where said first and second semiconductor switches are controlled by signals generated by the linear amplifier stage.

2. The regulating apparatus of claim 1 , wherein when said second semiconductor switch is activated, said second semiconductor switch and said inductor form a closed circuit such that the current stored in said inductor recirculates through said second semiconductor switch, and when said second semiconductor switch is deactivated said inductor is capable of delivering current to said output node.

3. The regulating apparatus according to claim 1 , wherein said linear amplifier stage comprises:

an error amplifier for receiving said reference signal and for generating an output signal indicative of the difference between said reference and said voltage level at said output node;

a linear amplifier coupled to said error amplifier so as to receive said output signal of said error amplifier, said linear amplifier being controlled by said output signal of said error amplifier; and

means for measuring current flowing into said linear amplifier from a power supply input terminal, whereby said means for measuring current does not increase the output impedance of said linear amplifier.

4. The regulating apparatus of claim 3 , wherein said signal controlling said second semiconductor switch is generated within said linear amplifier stage by a second comparator which monitors said output signal of said error amplifier and turns on said second semiconductor switch when the magnitude of the input signal to said second comparator falls below a predetermined level.

5. The regulating apparatus of claim 4 , wherein said second comparator exhibits a hysteretic characteristic with respect to the changing of its output state.

6. The regulating apparatus of claim 3 , wherein the control for said first semiconductor switch is generated within said linear amplifier stage by a first comparator which monitors the output of said means for measuring current and turns on said first semiconductor switch when the magnitude of the input signal in said first comparator exceeds a predetermined value.

7. The regulating apparatus of claim 6 , wherein said first comparator exhibits a hysteretic characteristic with respect to the changing of its output state.

8. The regulating apparatus of claim 3 , wherein said linear amplifier comprises an NPN transistor.

9. The regulating apparatus according to claim 3 , wherein an output stage of said linear amplifier comprises a first transistor and a second transistor, which are coupled to one another in a parallel configuration.

10. The regulating apparatus according to claim 9 , wherein the area of an emitter of said first transistor and the area of an emitter of said second transistor are different from each other.

11. The regulating apparatus according to claim 9 , wherein said output stage of said linear amplifier further comprises a transistor and a current mirror, wherein said transistor receives the output signal of said error amplifier as an input signal, said transistor having an output signal coupled to an input of said current mirror, said current mirror having an output coupled to an input of said first and second transistors coupled in parallel.

12. The regulating apparatus of claim 1 , wherein said first semiconductor switch comprises a PMOS transistor, and said second semiconductor switch comprises an NMOS transistor, said NMOS transistor having a body terminal coupled to said common node.

13. The regulating apparatus of claim 1 , wherein said diode comprises an active diode.

14. The regulating apparatus of claim 1 , further comprising a programmable output switching regulator having an output voltage signal, which is coupled to said linear amplifier stage and which operates as a supply voltage to said linear amplifier stage;

wherein said output voltage signal of said programmable output switching regulator equals an average of the value of the voltage signal input into said programmable output switching regulator.

15. The regulating apparatus according to claim 14 , wherein said voltage input into said programmable output switching regulator equals the sum of the voltage output by said linear amplifier stage and a reference voltage.

16. The regulating apparatus according to claim 15 , wherein said programmable output switching regulator is operable for reducing power dissipation in said linear amplifier stage when the value of the voltage output by said linear amplifier stage plus said reference voltage is less than the value of a supply voltage.

17. The regulating apparatus according to claim 15 , wherein said programmable output switching regulator is operable for preventing the output of said linear amplifier stage from clipping.