Method and apparatus for lockstep processing on a fixed-latency interconnect
View Patent ↗Methods of operating two or more devices in lockstep by generating requests at each device, comparing the requests, and forwarding matching requests to a servicing node are described and claimed. A redundant execution system using the methods is also described and claimed.
1. A method comprising:
simultaneously generating a first request at a first computer device to access a system resource and generating a second request at a second computer device, in communication with the first computer device, to access the system resource, the first computer device being closer to the system resource while the second computer device being farther from the system resource, wherein the computer devices are designated as closer and farther to indicate their position on a fixed-latency interconnect relative to the system resource;
receiving, at the first computer device that is closer to the system resource, the second request from the second computer device that is farther from the system resources to access the system resource over the fixed-latency interconnect;
comparing the first request to the second request;
if the first request matches the second request, merging the first request and the second request into a merged request and sending the merged request over the fixed-latency interconnect to the system resource from the first computer device; and
if the first request differs from the second request, generating a lockstep error and signaling a lockstep failure in response to the lockstep error.
2. The method of claim 1 wherein the first request and the second request are to obtain data from a memory.
3. The method of claim 1 wherein the first request and the second request are to send data to a component or receive data from the component, wherein the component is different from a plurality of devices operating in lockstep.
4. A processor comprising:
mapping logic to determine the relative position of a first processor core and a second processor core to system resources, wherein the first and second processor cores are coupled with an interconnection network, wherein the mapping logic further identifies which of the first and second processor cores is closer to the system resources, the first processor core being closer to the system resources and the second processor being farther from the system resources to access system resources;
request logic to generate a first request at the first processor core and a second request at the second processor core to access the system resources, wherein the request logic is further to coordinate the first and second requests from the first and second processing cores, respectively, to the system resources, the request logic is further to receive, at the first processor core that is closer to the system resources, the second request from the second processor core that is farther from the system resources; and
verification logic to compare the first request to the second request, wherein the request logic is further to merge the first and second requests into a merged request if the first request matches the second request, and to generate a lockstep error if the first request differs from the second request;
response logic to coordinate responses to the first and second processor cores and the system resources, the response logic is further to send the merged request to the system resources or signal a lockstep failure in response to the lockstep error.
5. The processor of claim 4 , further comprising:
lockstep disabling logic to disable lockstep logic elements.
6. The processor of claim 4 , further comprising:
lockstep recovery logic to synchronize the first and second processor cores.
7. The processor of claim 4 wherein the response logic is to receive a response at the first processor core;
allocate an acknowledgement buffer at the first processor core;
send the response to the second processor core; and
delay response processing until an acknowledgement is received from the second processor core.
8. A machine-readable medium that provides instructions that, when executed by a data processing device, cause the data processing device to perform operations comprising:
simultaneously generating a first request at a first computer device to access a system resource and generating a second request at a second computer device, in communication with the first computer device, to access the system resource, the first computer device being closer to the system resource while the second computer device being farther from the system resource;
receiving, at the first computer device that is closer to the system resources, the second request from the second computer device that is farther from the system resources to access the system resource over a fixed-latency interconnect;
comparing the first request to the second request;
if the first request matches the second request, merging the first request and the second request into a merged request and sending the merged request over the fixed-latency interconnect to the system resource from the first computer device; and
if the first request differs from the second request, generating a lockstep error and signaling a lockstep failure in response to the lockstep error.
9. The machine-readable medium of claim 8 wherein the first request and the second request are to obtain data from a memory.
10. The machine-readable medium of claim 8 wherein the first request and the second request are to send data to a component or receive data from the component, wherein the component is different from a plurality of devices operating in lockstep.