Cross-point RRAM memory array having low bit line crosstalk
View Patent ↗A cross-point RRAM memory array includes a word line array having an array of substantially parallel word lines therein and a bit line array having an array of substantially parallel bit lines therein, wherein said bit lines are substantially perpendicular to said word lines, and wherein a cross-point is formed between said word lines and said bit lines. A memory resistor located between said word lines and said bit lines at each cross-point. A high-open-circuit-voltage gain, bit line sensing differential amplifier circuit located on each bit line, including a feedback resistor and a high-open-circuit-voltage gain amplifier, arranged in parallel, wherein a resistance of the feedback resistors is greater than a resistance of any of the memory resistors programmed at a low resistance state.
1. A cross-point RRAM memory array comprising:
a word line array having an array of substantially parallel word lines therein;
a bit line array having an array of substantially parallel bit lines therein, wherein said bit lines are substantially perpendicular to said word lines, and wherein a cross-point is formed between said word lines and said bit lines;
a memory resistor located between said word lines and said bit lines at each cross-point; and
a high-open-circuit-voltage gain, bit line sensing differential amplifier circuit located on each bit line, including a feedback resistor and a high-gain amplifier, arranged in parallel, wherein a resistance of said feedback resistor is greater than a resistance of any of said memory resistors when said memory resistors are programmed at a low resistance state.
2. The RRAM memory array of claim 1 wherein, for adjacent bit lines, I 1 is a current through a first bit line, I 2 is a current through an adjacent, second bit line, and I 3 is a leakage current between the first bit line and the second bit line, and wherein I 3 is much smaller than I 2 or I 1 .
3. The RRAM memory array of claim 1 wherein, for adjacent bit lines, V i1 is a voltage passing through a memory resistor from a first word line to a first bit line, V i2 is a voltage passing through an adjacent memory resistor to a second bit line, where
V
i
1
=
V
01
A
and
V
i
2
=
V
02
A
are the high-gain bit line sensing amplifier circuit input voltages, wherein, when A is larger than 100, V i1 and V i2 are negligibly small compared to V at the word line input.
4. A cross-point RRAM memory array comprising:
a word line array having an array of substantially parallel word lines therein;
a bit line array having an array of substantially parallel bit lines therein, wherein said bit lines are substantially perpendicular to said word lines, and wherein a cross-point is formed between said word lines and said bit lines;
a memory resistor located between said word lines and said bit lines at each cross-point; and
a high-open-circuit-voltage gain, bit line sensing differential amplifier circuit located on each bit line, including a feedback resistor and a high-gain amplifier, arranged in parallel, wherein a resistance of said feedback resistor is smaller than a resistance of any of said memory resistors when said memory resistors are programmed at a high resistance state.
5. The RRAM memory array of claim 4 wherein, for adjacent bit lines, I 1 is a current through a first bit line, I 2 is a current through an adjacent, second bit line, and I 3 is a leakage current between the first bit line and the second bit line, and wherein I 3 is much smaller than I 2 or I 1 .
6. The RRAM memory array of claim 4 wherein, for adjacent bit lines, V i1 is a voltage passing through a memory resistor from a first word line to a first bit line, V i2 is a voltage passing through an adjacent memory resistor to a second bit line, where
V
i
1
=
V
01
A
and
V
i
2
=
V
02
A
are the high-gain bit line sensing amplifier circuit input voltages, wherein, when A is larger than 100, V i1 and V i2 are negligibly small compared to V at the word line input.