Memory array with global bitline domino read/write scheme

1. A memory circuit comprising:

a plurality of cells, wherein each of the cells is configured to store a bit of data;

a plurality of local bitlines, wherein each of the plurality of cells is coupled to one of the plurality of local bitlines, wherein each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path, wherein the signal path and the complementary signal path of each of the plurality of local bitlines are cross-coupled by a pair of transistors, and wherein each of the plurality of cells is coupled to one of the plurality of local bitlines; and

a pull circuit, wherein the pull circuit is configured to, in a first state, pull up the signal path and pull down the complementary signal path, and wherein in a second state, the pull circuit is configured to pull down the signal path and pull up the complementary signal path, wherein the pull circuit includes:

a first pulldown line operatively coupled to the signal path and the complementary signal path, wherein the first pulldown line, when activated, is configured to cause the complementary signal path to be pulled down to a reference voltage and the signal path to be pulled up to a logic voltage; and

a second pulldown line operatively coupled signal path an the complementary signal path, wherein the second pulldown line, when activated, is configured to cause the signal path to be pulled down to a reference voltage and the complementary signal path to be pulled up to a logic voltage.

2. The memory circuit as recited in claim 1 , wherein the memory circuit further includes a first precharge line and a second precharge line, wherein the first precharge line, when energized, causes a first one of the plurality of local bitlines to be charged to a logic high voltage, and wherein the second precharge line, when energized, causes a second one of the plurality of local bitlines to be charged to a logic high voltage.

3. The memory circuit as recited in claim 2 , wherein the memory circuit is configured such that a precharge is performed upon completion of a write cycle.

4. The memory circuit as recited in claim 2 , wherein the memory circuit is configured such that a read operation, a write operation, and a precharge operation are all completed in a single memory cycle.

5. The memory circuit as recited in claim 4 , wherein the memory circuit includes a NAND gate coupled to receive a global bitline input and a complementary global bitline input, and wherein the NAND gate is configured to assert a signal indicating completion of the read operation when one of the global bitline input and the complementary global bitline input falls to a logic low voltage.

6. The memory circuit as recited in claim 2 , wherein the memory circuit is configured such that a read and precharge operations are completed within a first memory cycle and wherein write and precharge operations are completed within a second memory cycle.

7. The memory circuit as recited in claim 2 , wherein the circuit is configured to perform read and write operations during a high portion of a clock cycle and precharge operations during a low portion of a clock cycle, and wherein the circuit is configured such that crowbar currents are avoided even if write and precharge operations overlap.

8. The memory circuit as recited in claim 1 , wherein the memory circuit includes an intermediate bitline operatively coupled to each of the plurality of local bitlines in a one-hot multiplexer arrangement.

9. The memory circuit as recited in claim 8 , wherein the intermediate bitline is operatively coupled to a global bitline, wherein the global bitline is a single ended bitline.

10. The memory circuit as recited in claim 1 , wherein each of the plurality of local bitlines is operatively coupled to a global bitline, wherein the global bitline is a differential bitline having a global bitline signal path and a complementary global bitline signal path.