Thin film transistor array panel
View Patent ↗A thin film transistor array panel is provided, which includes a substrate; a plurality of semiconductor islands formed on the substrate, the plurality of semiconductor islands including a plurality of first and second extrinsic regions, and a plurality of intrinsic regions; a gate insulating layer covering the semiconductor islands; a plurality of gate lines including a plurality of gate electrodes overlapping the intrinsic regions and formed on the gate insulating layer; a plurality of data lines connected to the first extrinsic regions and formed on the gate insulating layer; and a plurality of pixel electrodes connected to the second extrinsic regions, wherein a plurality of protrusions are formed on the surfaces of the semiconductor islands, and a length of a semiconductor island is a multiple of the a distance between at least two protrusions.
1. A thin film transistor array panel, comprising:
a substrate;
a plurality of semiconductor islands formed on the substrate, the plurality of semiconductor islands including a plurality of first extrinsic regions, a plurality of second extrinsic regions, and a plurality of intrinsic regions;
a gate insulating layer covering the semiconductor islands;
a plurality of gate lines formed on the gate insulating layer and including a plurality of gate electrodes overlapping the intrinsic regions;
a plurality of data lines formed on the gate insulating layer and connected to the plurality of first extrinsic regions; and
a plurality of pixel electrodes connected to the plurality of second extrinsic regions,
wherein a plurality of protrusions are formed on the surfaces of semiconductor islands with the same material as the semiconductor islands, and a length of a semiconductor island divided by a distance between two protrusions of the plurality of protrusions is substantially equal to an integer,
wherein the protrusions are spaced substantially at uniform intervals, and wherein a number of the protrusions formed on each semiconductor island is the same, and
wherein the protrusions formed on each semiconductor island extend across the entire semiconductor island in a direction perpendicular to a length direction of the semiconductor islands.
2. The thin film transistor array panel of claim 1 , wherein the semiconductor islands are crystallized by sequential lateral solidification.
3. The thin film transistor array panel of claim 1 , further comprising:
a plurality of storage electrode lines formed parallel the gate lines.
4. The thin film transistor array panel of claim 1 , further comprising:
a blocking layer formed between the substrate and the semiconductor islands.
5. The thin film transistor array panel of claim 1 , further comprising:
a passivation layer formed between the plurality of pixel electrodes and the plurality of gate and the data lines.
6. The thin film transistor array panel of claim 5 , further comprising:
an interlayer insulating layer formed between the plurality of gate lines and the plurality of data lines; and
a plurality of output electrodes formed between the passivation layer and the interlayer insulating layer and connecting the plurality of pixel electrodes to the plurality of second extrinsic regions.
7. The thin film transistor array panel of claim 6 , wherein the plurality of second extrinsic regions includes a plurality of drain regions.
8. The thin film transistor array panel of claim 1 , further comprising:
a plurality of partitions formed on the plurality of pixel electrodes; and
a plurality of light emitting members formed on the plurality of pixel electrodes and disposed in openings defined by the plurality of partitions.
9. The thin film transistor array panel of claim 1 , wherein the distance is between any two adjacent protrusions of the plurality of protrusions.
10. A thin film transistor array panel, comprising:
a substrate;
a plurality of semiconductor islands formed on the substrate, the plurality of semiconductor islands including a plurality of first extrinsic regions, a plurality of second extrinsic regions, and a plurality of intrinsic regions;
a plurality of gate lines formed on the substrate and including a plurality of gate electrodes overlapping the intrinsic regions;
a plurality of data lines formed on the substrate and connected to the plurality of first extrinsic regions; and
a plurality of pixel electrodes connected to the plurality of second extrinsic regions,
wherein a plurality of protrusions are formed on the surfaces of semiconductor islands with the same material as the semiconductor islands, and a length of a semiconductor island divided by a distance between two protrusions of the plurality of protrusions is substantially equal to an integer,
wherein the protrusions are spaced substantially at uniform intervals,
wherein a number of the protrusions formed on each semiconductor island is the same, and
wherein the protrusions formed on each semiconductor island extend across the entire semiconductor island in a direction perpendicular to a length direction of the semiconductor islands.
11. The thin film transistor array panel of claim 10 , wherein the semiconductor islands are crystallized by sequential lateral solidification.
12. The thin film transistor array panel of claim 10 , further comprising:
a blocking layer formed between the substrate and the semiconductor islands.
13. The thin film transistor array panel of claim 10 , further comprising:
a plurality of partitions formed on the plurality of pixel electrodes; and a plurality of light emitting members formed on the plurality of pixel electrodes and disposed in openings defined by the plurality of partitions.
14. The thin film transistor array panel of claim 10 , wherein the distance is between any two adjacent protrusions of the plurality of protrusions.