Semiconductor package form within an encapsulation
View Patent ↗Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.
1. A semiconductor package comprising:
a semiconductor chip comprising a top surface and a bottom surface, the bottom surface having a plurality of bumps formed thereon;
redistribution layer patterns formed under the semiconductor chip, comprising a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part;
a patterned insulating layer formed below the redistribution layer patterns, exposing at least a part of the second part of the redistribution layer patterns;
an encapsulation layer exposing a bottom surface of the patterned insulating layer and surrounding the semiconductor chip, the bumps, and the redistribution layer patterns; and
an organic insulating layer interposed between the redistribution layer patterns and the semiconductor chip, having electrically conductive particles distributed in the organic insulating layer,
wherein the electrically conductive particles are interposed between top surfaces of the first parts of the redistribution layer patterns and bottom surfaces of the bumps to directly contact the top surfaces of first parts of the redistribution layer patterns and the bottom surfaces of the bumps.
2. The semiconductor package of claim 1 , wherein a surface area of the second part of each of the redistribution layer patterns is greater than a surface area of the first part of each of the redistribution layer patterns.
3. The semiconductor package of claim 1 , wherein a diameter of each of the bumps is in the range of 5 to 200 μm.
4. The semiconductor package of claim 1 , wherein each of the redistribution layer patterns comprises one or more layers of the group consisting of a gold layer, a nickel layer, and a copper layer.
5. The semiconductor package of claim 1 , wherein the second parts of the redistribution layer patterns are land patterns to be connected to an external device.