Radio receiver, system on a chip integrated circuit and methods for use therewith
View Patent ↗A system on a chip integrated circuit includes an analog front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital signal. A digital clock generator generates a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals. The digital clock frequency, and integer multiples of the digital clock frequency, are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A digital section converts the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal.
1. A system on a chip integrated circuit comprising:
an analog front end to:
receive a radio signal that includes a plurality of analog channel signals, wherein a first channel signal of the plurality of analog channel signals has a first carrier frequency;
convert the first channel signal into a first digital signal; and
output the first digital signal;
a digital clock generator to generate a first digital clock signal corresponding to the first channel signal, wherein the first digital clock signal has a first digital clock frequency that is selected based on the first digital signal; and
a digital section operably coupled to the analog front end, the digital section to receive the first digital signal and to convert the received first digital signal into a first audio signal, wherein the conversion is based on the first digital clock signal;
wherein each of the first digital clock frequency and integer multiples of the first digital clock frequency differs from the first carrier frequency.
2. The system on a chip integrated circuit of claim 1 , further comprising:
a channel selector to produce a first control signal that corresponds to the first channel signal; and
a local oscillator operably coupled to the analog front end and to a reference oscillator, the local oscillator to generate a first local oscillation signal based on the first control signal;
wherein the digital clock generator includes a divider to divide the first local oscillation signal to produce the first digital clock signal.
3. The system on a chip integrated circuit of claim 2 , wherein the divider is to divide the first local oscillation signal by an integer.
4. The system on a chip integrated circuit of claim 3 , wherein the integer is equal to six.
5. The system on a chip integrated circuit of claim 2 , wherein the divider includes a fractional divider.
6. The system on a chip integrated circuit of claim 1 , wherein the first digital clock frequency is substantially equal to two-thirds of the first carrier frequency.
7. The system on a chip integrated circuit of claim 1 , wherein the first digital clock frequency is less than the first carrier frequency.
8. The system on a chip integrated circuit of claim 1 , wherein the received radio signal is one of a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, and a broadcast cable signal.
9. The system on a chip integrated circuit of claim 1 , wherein the analog front end includes an in-phase signal path and a quadrature-phase signal path.
10. A method comprising:
receiving a radio signal having a plurality of analog channel signals at an integrated circuit, wherein a first channel signal of the plurality of analog channel signals has a first carrier frequency;
converting the first channel signal of the plurality of analog channel signals into a first digital signal;
generating a first digital clock signal having a first digital clock frequency that is selected based at least in part on the first digital signal;
converting the first digital signal into a first audio signal, wherein the conversion is executed based on the first digital clock signal;
wherein the first digital clock frequency and integer multiples of the first digital clock frequency differ from the first carrier frequency.
11. The method of claim 10 , further comprising:
producing a first control signal that corresponds to the first channel signal; and
generating a first local oscillation signal based on the first control signal;
wherein receiving includes mixing the received radio signal and the first local oscillation signal; and
wherein generating the first digital clock signal includes dividing the first local oscillation signal to produce the first digital clock signal.
12. The method of claim 11 , wherein dividing comprises dividing by an integer.
13. The method of claim 12 , wherein the integer is equal to 6.
14. The method of claim 10 , wherein the first digital clock frequency is substantially equal to two-thirds of the first carrier frequency.
15. The method of claim 10 , wherein the first digital clock frequency has a first digital clock frequency that is less than the first carrier frequency and is greater than zero.
16. The method of claim 10 , wherein the received radio signal is one of a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, and a broadcast cable signal.
17. The method of claim 10 , wherein receiving further comprises processing the received radio signal along an in-phase signal path and processing the received radio signal along a quadrature-phase signal path.