IP Library Granted Patent US 7,492,613
Granted Patent B2
US 7,492,613 · App. 11/288,726 · Granted Feb 17, 2009

Control circuit of power converter having adaptive bias for detecting reflected voltage of transformer

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Quick Facts
Patent No.
US 7,492,613
App. No.
11/288,726
Granted
Feb 17, 2009
Kind
B2
Abstract

A control circuit for detecting the reflected voltage of a transformer is provided. A detection circuit is developed for sampling the reflected voltage. Because the pulse width of the reflected voltage is narrower at light load, a bias circuit is utilized for producing a bias signal to help the reflected voltage detection. Furthermore, a blanking circuit ensures a minimum pulse width of the reflected voltage.

Claims (27)

1. A control circuit of a power converter, comprising:

a switch coupled to a transformer for switching the transformer;

a detection circuit coupled to the transformer for detecting a reflected voltage of the transformer and generating a feedback signal in accordance with the reflected voltage;

a switching circuit generating a control signal to control the switch and to regulate the output of the power converter in response to the feedback signal; and

an adjust circuit generating an adjust signal proportionally to the feedback signal, wherein the detection circuit includes a bias circuit for receiving the adjust signal and generating a bias signal proportionally to the adjust signal, the bias signal is coupled to the input of the detection circuit for the detection of the reflected voltage.

2. The control circuit of the power converter as claimed in claim 1 , wherein the switching circuit comprises a blanking circuit for generating a blanking signal in response to the control signal, in which the blanking signal ensures a minimum on time of the control signal once the control signal is switched on.

3. The control circuit of the power converter as claimed in claim 1 , the bias circuit comprising:

a transistor coupled to the input of the detection circuit for generating the bias signal; and

a resistor coupled to receive the adjust signal for generating a bias voltage to control the transistor,

wherein the bias signal is generated proportionally to the bias voltage.

4. The control circuit of the power converter as claimed in claim 1 , the detection circuit further comprising:

a waveform detector for detecting the reflected voltage and generating a sampled signal in accordance with the reflected voltage; and

an error amplifier having a reference signal for generating a feedback signal in response to the sampled signal.

5. The control circuit of the power converter as claimed in claim 4 , the waveform detector comprising

a current source;

a buffer transistor having a first terminal connected to the current source;

an amplifier having a positive input connected to the input of the detection circuit for detecting the reflected voltage; the output of the amplifier coupled to control the second terminal of the buffer transistor; the negative input of the amplifier connected to a third terminal of the buffer transistor;

a first capacitor connected to the third terminal of the buffer transistor,

a first switch connected in parallel with the first capacitor for discharging the first capacitor periodically;

a second capacitor generating the sampled signal in accordance with the reflected voltage; and

a second switch periodically sampling the signal of the first capacitor and storing into the second capacitor.

6. The control circuit of the power converter as claimed in claim 1 , the adjust circuit comprising:

a first amplifier having a positive input supplied by a threshold voltage;

a second amplifier having a positive input connected to the feedback signal, and the negative input of the second amplifier connected to the output of the second amplifier;

a first transistor coupled to the output of the first amplifier for generating a first transistor current in response to the threshold voltage and the feedback voltage;

a first resistor connected from the first transistor to the output of the second amplifier; and

a second transistor and a third transistor forming a current mirror for generating the adjust signal in accordance with the first transistor current.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded Jun 8, 2016
From: SYSTEM GENERAL CORP.
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 038906/0030 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2005
From: YANG, TA-YUNG; LI, CHUH-CHING; TSAO, FENG CHENG
To: SYSTEM GENERAL CORP.
Reel/Frame 017293/0562 →