Redundant synchronous clock distribution system
View Patent ↗A redundant synchronous clock distribution system is provided comprising at least a first and a second clock module and first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system. Each of the first and second clock modules are adapted to act as a master clock module or a slave clock module. A clock switchover module is adapted to switch each of the first and second clock modules to change between the master mode and the slave mode. The clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part, wherein the first circuit part is located on the first clock module and the second circuit part is located on the second clock module.
1. A redundant synchronous clock distribution system, comprising:
at least first and second clock modules,
first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system,
each of the first and second clock modules adapted to act, in a master mode, as a master clock module for providing one of said clock distribution branches with an active clock signal, and adapted to act, in a slave mode, as a slave clock module for providing the respective other of said clock distribution branches with a standby clock signal,
a clock switchover module adapted to switch each of the first and second clock modules to change between the master mode and the slave mode,
wherein said clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part,
said first circuit part of said flip-flop-circuit located on said first clock module and said second circuit part of said flip-flop-circuit located on said second clock module,
wherein said first circuit part of said flip-flop-circuit comprises a first logical gate,
said first logical gate having a first input adapted to receive a first request signal which indicates a demand to change between the master mode and the slave mode,
said first logical gate having a second input coupled to said second circuit part of the flip-flop-circuit,
said first logical gate having an output adapted to output a first command signal which indicates the current master or slave status of the first clock module.
2. The redundant synchronous clock distribution system according to claim 1 , wherein said flip-flop-circuit is configured as a Reset-Set flip-flop-circuit.
3. A redundant synchronous clock distribution system, comprising:
at least first and second clock modules,
first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system,
each of the first and second clock modules adapted to act, in a master mode, as a master clock module for providing one of said clock distribution branches with an active clock signal, and adapted to act, in a slave mode, as a slave clock module for providing the respective other of said clock distribution branches with a standby clock signal,
a clock switchover module adapted to switch each of the first and second clock modules to change between the master mode and the slave mode,
wherein said clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part,
said first circuit part of said flip-flop-circuit located on said first clock module and said second circuit part of said flip-flop-circuit located on said second clock module,
wherein said second circuit part of said flip-flop-circuit comprises a second logical gate,
said second logical gate having a first input adapted to receive a second request signal which indicates a demand to change between the master mode and the slave mode,
said second logical gate having a second input coupled to the first circuit part of the flip-flop-circuit,
said second logical gate having an output adapted to output a second command signal which indicates the current master or slave status of the second clock module.
4. The redundant synchronous clock distribution system according to claim 3 , wherein said flip-flop-circuit is configured as a Reset-Set flip-flop-circuit.
5. A redundant synchronous clock distribution system, comprising:
at least first and second clock modules,
first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system,
each of the first and second clock modules adapted to act, in a master mode, as a master clock module for providing one of said clock distribution branches with an active clock signal, and adapted to act, in a slave mode, as a slave clock module for providing the respective other of said clock distribution branches with a standby clock signal,
a clock switchover module adapted to switch each of the first and second clock modules to change between the master mode and the slave mode,
wherein said clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part,
said first circuit part of said flip-flop-circuit located on said first clock module and said second circuit part of said flip-flop-circuit located on said second clock module,
wherein said switchover module is provided with a first detection circuit which is adapted to detect a floating or open interconnection between the first and the second circuit parts of the flip-flop-circuit.
6. The redundant synchronous clock distribution system according to claim 5 , wherein
the first detection circuit comprises a first resistor and a first operational amplifier, a first voltage terminal, and a second voltage terminal,
a to be detected interconnection coupled to the first voltage terminal via the first resistor and to a first input of the first operational amplifier,
the first operational amplifier having a second input coupled to the second voltage terminal,
the first operational amplifier having an output adapted to output a detection signal of the first detection circuit.
7. The redundant synchronous clock distribution system according to claim 5 , wherein
said flip-flop-circuit is configured as a Reset-Set flip-flop-circuit.
8. A redundant synchronous clock distribution system, comprising:
at least first and second clock modules,
first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system,
each of the first and second clock modules adapted to act, in a master mode, as a master clock module for providing one of said clock distribution branches with an active clock signal, and adapted to act, in a slave mode, as a slave clock module for providing the respective other of said clock distribution branches with a standby clock signal,
a clock switchover module adapted to switch each of the first and second clock modules to change between the master mode and the slave mode,
wherein said clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part,
said first circuit part of said flip-flop-circuit located on said first clock module and said second circuit part of said flip-flop-circuit located on said second clock module,
wherein said switchover module is provided with a second detection circuit which is adapted to detect a short-circuited interconnection between the first and the second circuit parts of the flip-flop-circuit.
9. The redundant synchronous clock distribution system according to claim 8 , wherein
the second detection circuit comprises a potential divider, a second operational amplifier, a second resistor, and a third voltage terminal,
the potential divider coupled into a to be detected interconnection, the potential divider having a first output coupled to a first input of the second operational amplifier, and having a second output coupled to a second input of the second operational amplifier,
the first input of the second operational amplifier coupled to the third voltage terminal via the second resistor,
the second operational amplifier having an output adapted to output a detection signal of the second detection circuit.
10. The redundant synchronous clock distribution system according to claim 8 , wherein said flip-flop-circuit is configured as a Reset-Set flip-flop-circuit.
11. A redundant synchronous clock distribution system, comprising:
at least first and second clock modules,
first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system,
each of the first and second clock modules adapted to act, in a master mode, as a master clock module for providing one of said clock distribution branches with an active clock signal, and adapted to act, in a slave mode, as a slave clock module for providing the respective other of said clock distribution branches with a standby clock signal,
a clock switchover module adapted to switch each of the first and second clock modules to change between the master mode and the slave mode,
wherein said clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part,
said first circuit part of said flip-flop-circuit located on said first clock module and said second circuit part of said flip-flop-circuit located on said second clock module,
wherein the flip-flop-circuit comprises a trail master request circuit adapted to compensate for a signal delay of signals transmitted between the first and second circuit parts of the flip-flop-circuit to prevent output signal oscillations of the flip-flop-circuit.
12. The redundant synchronous clock distribution system according to claim 11 , wherein said flip-flop-circuit is configured as a Reset-Set flip-flop-circuit.
13. A redundant synchronous clock distribution system, comprising:
at least first and second clock modules,
first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system,
each of the first and second clock modules adapted to act, in a master mode, as a master clock module for providing one of said clock distribution branches with an active clock signal, and adapted to act, in a slave mode, as a slave clock module for providing the respective other of said clock distribution branches with a standby clock signal,
a clock switchover module adapted to switch each of the first and second clock modules to change between the master mode and the slave mode,
wherein said clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part,
said first circuit part of said flip-flop-circuit located on said first clock module and said second circuit part of said flip-flop-circuit located on said second clock module,
wherein the flip-flop-circuit provides for a buffer circuit with life insertion capability adapted to provide a predetermined signal status when a clock module is inserted.
14. The redundant synchronous clock distribution system according to claim 13 , wherein said flip-flop-circuit is configured as a Reset-Set flip-flop-circuit.