TFT array substrate and the fabrication method thereof
View Patent ↗A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.
1. A thin film transistor (TFT) array substrate, comprising:
a gate electrode connected to a gate line;
a source electrode connected to a data line crossing the gate line to define a pixel region;
a drain electrode which is opposite to the source electrode with a channel in between;
a semiconductor layer defining the channel between the source electrode and the drain electrode;
a pixel electrode in the pixel region and connected to the drain electrode;
a channel passivation layer formed only at a predetermined location corresponding to the channel of the semiconductor layer;
a gate pad extending from the gate line
a data pad connected to the data line, where a transparent conductive pattern is formed;
a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad, and
a transparent conductive pattern formed on the drain electrode,
wherein the transparent conductive pattern is formed of the same material as the pixel electrode,
wherein the gate pad includes,
a gate pad lower electrode connected to the gate line;
a contact hole penetrating the gate insulating layer and the semiconductor pattern to expose the gate pad lower electrode; and
a gate pad upper electrode connected to the gate pad lower electrode, the semiconductor layer and a data metal pattern through the contact hole,
wherein the gate pad upper electrode is formed on the data metal pattern,
wherein the gate pad upper electrode is formed of the same material as the transparent conductive pattern.
2. The TFT array substrate according to claim 1 , wherein the channel passivation layer is formed of one of a silicon nitride (SiNx) and a silicon oxide (SiOx).
3. The TFT array substrate according to claim 1 , wherein the semiconductor layer includes:
an active layer defining the channel between the source electrode and the drain electrode; and
an ohmic contact layer formed between the source/drain electrodes and the active layer.
4. The TFT array substrate according to claim 1 , further comprising a storage capacitor including the gate line overlapping the pixel electrode, wherein the gate insulating layer is in between the gate line and the pixel electrode.
5. The TFT array substrate according to claim 1 , wherein the data pad is connected to the data line and the data lower electrode through a jumping electrode of a transparent material.
6. The TFT array substrate according to claim 1 , wherein the data pad includes:
a data pad lower electrode formed of a gate material; and
a data pad upper electrode connected through a contact hole to the data pad lower electrode with a gate insulating layer interposed therebetween.
7. A TFT array substrate comprising:
a gate electrode connected to a gate line;
a source electrode connected to a data line crossing the gate line to define a pixel region;
a drain electrode which is opposite to the source electrode with a channel in between;
a semiconductor layer defining the channel in between the source electrode and the drain electrode;
a pixel electrode formed at the pixel region, directly connected to the drain electrode;
a channel passivation layer formed at a predetermined location corresponding to the channel of the semiconductor layer to protect the semiconductor layer defining the channel;
a gate pad extended from the gate line where a semiconductor pattern and a transparent conductive pattern are formed;
a data pad connected to the data line where the transparent conductive pattern is formed;
even/odd data lines that apply signals to the data pad;
an electrostatic passivation line pattern connected to one of the even and odd data lines, arranged to be separated by a predetermined distance; and
an outer shorting bar connected to each of one of the even and odd data lines.
8. The TFT array substrate according to claim 7 , further comprising a jumping electrode to connect the data line to the data pad.
9. The TFT array substrate according to claim 7 , wherein the electrostatic protection line pattern is connected to the outer shorting bar so as to form an equipotential between the even and odd data lines.