TFT array substrate and the fabrication method thereof

1. A TFT (thin film transistor) array substrate comprising:

a gate electrode connected to a gate line;

a source electrode connected to a data line;

a pixel region defined by crossing the gate line and the data line;

a drain electrode facing the source electrode with a channel between;

a semiconductor layer forming the channel in between the source electrode and the drain electrode;

a pixel electrode in the pixel region and contacting the drain electrode, the pixel electrode directly on a gate insulating layer;

a channel passivation layer formed the semiconductor layer;

a gate pad with a gate pad lower electrode that extends from the gate line;

a data pad having a data pad lower electrode separated from the data line, wherein the data pad is electrically connected to the data line and the data pad lower electrode through a jumping electrode, wherein the data pad includes the data pad lower electrode formed of the same material as the gate electrode and a data pad upper electrode that connects through a contact hole to the data pad lower electrode with a gate insulating layer in between, and

a plurality of transparent conductive pattern formed of the same material as the pixel electrode on the data line, the source and drain electrodes, respectively,

wherein a space between the transparent conductive pattern formed on the source electrode and the transparent conductive pattern formed on the drain electrode are 4-5 μm, and a space between the transparent conductive pattern formed on the data line and the pixel electrode are 4-5 μm,

wherein the pixel electrode directly contacts an upper surface of the gate insulating layer.

2. The TFT array substrate according to claim 1 , wherein the channel passivation layer is formed of one of SiNx and SiOx.

3. The TFT array substrate according to claim 1 , wherein the semiconductor layer includes:

an active layer forming the channel between the source electrode and the drain electrode; and

an ohmic contact layer between the source/drain electrodes and the active layer.

4. The TFT array substrate according to claim 1 , further including a storage capacitor formed the gate line and the pixel electrode overlapping the gate line with a gate insulating layer in between.

5. The TFT array substrate according to claim 1 , wherein the gate pad includes:

a contact hole passing through the gate insulating layer to expose the gate pad lower electrode; and

a gate pad upper electrode connected to the gate pad lower electrode through the contact hole.

6. The TFT array substrate according to claim 1 , wherein the jumping electrode is formed of a transparent material.

7. A TFT (thin film transistor) array substrate comprising:

a gate electrode connected to a gate line;

a source electrode connected to a data line;

a pixel region defined by crossing the gate line and the data line;

a drain electrode facing the source electrode with a channel in between;

a semiconductor layer forming the channel between the source electrode and the drain electrode;

a pixel electrode disposed in the pixel region and contacting the drain electrode;

a channel passivation layer formed the semiconductor layer;

a gate pad having a gate pad lower electrode that extends from the gate line;

a data pad having a data pad lower electrode separated from the data line;

even and odd data lines that apply a signal to the data pad, wherein the even and odd data lines is formed of the same material as the gate electrode, wherein the even and odd data lines are connected to a first shorting bar and a second shorting bar, respectively, wherein the first shorting bar is formed of the same material as the gate electrode and the second shorting bar is formed of the same material as the drain electrode;

a static electricity prevention line pattern connected to one of the even and odd data lines, and

a plurality of transparent conductive pattern formed of the same material as the pixel electrode on the data line, the source and drain electrodes, respectively,

wherein a space between the transparent conductive pattern formed on the source electrode and the transparent conductive pattern formed on the drain electrode are 4-5 μm, and a space between the transparent conductive pattern formed on the data line and the pixel electrode are 4-5 μm,

wherein the even data lines have an H-shaped ground line.

8. The TFT array substrate according to claim 7 , wherein the first and second shorting bars are cut and removed.