Data processing apparatus, program, and method for testing a secured circuit and maintaining confidentiality of the circuit

1. A data processing apparatus incorporating a processor and a tamper-resistant secured circuit, wherein:

said processor outputs a test start instruction to said tamper-resistant secured circuit;

said tamper-resistant secured circuit is provided with a test means for conducting a self-diagnostic test on the tamper-resistant secured circuit and, when said test start instruction is received from said processor, said test means conducts a self-diagnostic test of the tamper-resistant secured circuit and outputs a test result indicating whether the tamper-resistant secured circuit is normal or not to said processor;

wherein when said tamper-resistant secured circuit performs a normal operation other than said self-diagnostic test, on condition that data input to said tamper-resistant secured circuit matches with any one of a predetermined plurality of formats regulated in advance, said test means brings said secured circuit to perform processing using the input data; while when performing said self-diagnostic test, on condition that the data input to said tamper-resistant secured circuit matches with a predetermined part of formats among said predetermined plurality of formats, said test means performs said self-diagnostic test by using the input data.

2. A data processing apparatus as set forth in claim 1 , wherein:

said self-diagnostic test comprises a plurality of test modules, and

said test means approves data exchange with elements outside of said tamper-resistant secured circuit when executing one of said test modules that is among a predetermined part of said plurality of test modules, while said test means prohibits data exchange with elements outside of said secured circuit when executing one of said test modules that is not among said predetermined part of said plurality of test modules.

3. A secured circuit comprising:

an interface for receiving as an input a test start instruction and outputting a test result indicating whether said secured circuit is normal or not; and

a test means for conducting a self-diagnostic test of the secured circuit when receiving said test start instruction via said interface and outputting a test result indicating whether the secured circuit is normal or not via said interface,

wherein when said secured circuit performs a normal operation other than said self-diagnostic test, on condition that data input to said secured circuit matches with any one of a predetermined plurality of formats regulated in advance, said test means brings said secured circuit to perform processing by using the input data; while in an operation of said self-diagnostic test, on condition that the data input to said secured circuit matches with a predetermined part of formats among said predetermined plurality of formats, the test means performs said self-diagnostic test by using the input data.

4. A secured circuit as set forth in claim 3 , wherein

said self-diagnostic test comprises a plurality of test modules, and

said test means approves data exchange with elements outside of said secured circuit via said interface when executing one of said test modules that is among a predetermined part of said plurality of test modules, while said test means prohibits data exchange with elements outside of said secured circuit via said interface when executing one of said test modules that is not among said predetermined part of said plurality of test modules.

5. A computer program product stored on a computer-readable medium and configured for execution by a tamper-resistant secured circuit, comprising:

a first routine for receiving a test start instruction as input;

a second routine for conducting a self-diagnostic test on said tamper-resistant secured circuit in accordance with said test start instruction input in said first routine,

wherein conducting said self-diagnostic test comprises executing a plurality of test modules, and

wherein the computer program determines whether each executed test module is permitted to exchange data with elements outside the tamper-resistant secured circuit; and

a third routine for outputting a test result indicating whether the tamper-resistant secured circuit is normal or not based on said self-diagnostic test performed in said second routine.

6. A data processing method for testing whether a tamper-resistant secured circuit is normal or not by using a processor and the tamper-resistant secured circuit, including:

a first step that said processor transmits a test start instruction to said tamper-resistant secured circuit;

and a second step for conducting a self-diagnostic test of the tamper-resistant secured circuit in accordance with said test start instruction transmitted in said first step,

wherein conducting said self-diagnostic test comprises executing a plurality of test modules, and

wherein the tamper-resistant secured circuit determines whether each executed test module is permitted to exchange data with elements outside the tamper-resistant secured circuit; and

a third step for outputting a test result indicating whether the tamper-resistant secured circuit is normal or not to said processor.