Method of forming dual interconnects in manufacturing MRAM cells

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 7,381,574
App. No.: 11/289,787
Granted: Jun 3, 2008
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on the magnetoresistive junction element; a second non-conductive layer above the first non-conductive layer in regions over the hard mask and a second of the metallic lines; a third non-conductive layer disposed above the hard mask; and a fourth non-conductive layer disposed on the third non-conductive layer. The method further includes partially opening first and second trenches to uncover the second non-conductive layer above the hard mask and second metallic line, respectively; fully opening the first and second trenches to uncover the hard mask and second metallic line, respectively; and filling the first and second trenches with conductive material.

Claims (27)

1. A method of forming dual interconnects in manufacturing a magnetoresistive memory cell, the method comprising:

providing an intermediate product comprising: a semiconductor substrate including active structures on a surface thereof at least one metallization layer comprising a plurality of metallic lines disposed above the active structures of the semiconductor substrate; a first non-conductive layer comprising a non-conductive material disposed above the metallization layer and including a via contact for conductively contacting a first one of the metallic lines; a magnetoresistive junction element disposed above the first non-conductive layer and conductively connected to the via contact; a metallic hard mask disposed on the magnetoresistive junction element and conductively connected therewith; a second non-conductive layer comprising a non-conductive material disposed above the first non-conductive layer at least in a region over the hard mask and at least in a region over a second one of the metallic lines of the metallization layer; a third non-conductive layer comprising a non-conductive material having etch-selectivity as to the second non-conductive layer disposed at least in a region above the hard mask; and a fourth non-conductive layer disposed at least on the third non-conductive layer;

partially opening a first trench to uncover the second non-conductive layer at least above a portion of the hard mask and partially opening a second trench to uncover the second non-conductive layer at least above a portion of the second metallic line in a same opening operation;

fully opening the first trench to uncover the hard mask;

fully opening the second trench to uncover the second metallic line, wherein fully opening the first trench and fully opening the second trench are performed in a same opening operation;

filling the first trench with conductive material; and

filling the second trench with conductive material.

2. The method of claim 1 , wherein filling of the first trench with conductive material and filling of the second trench with conductive material are performed in a same filling operation.

3. The method of claim 1 , further comprising performing a cleaning operation using the third non-conductive layer as a protecting layer.

4. The method of claim 1 , wherein the third non-conductive layer has etch-selectivity with respect to the fourth non-conductive layer.

5. The method of claim 4 , further comprising partially opening the first trench to uncover the third non-conductive layer at least above a portion of the hard mask and partially opening the second trench to uncover the third non-conductive layer at least above a portion of the second metallic line in a same opening operation.

6. The method of claim 1 , wherein the hard mask has a thickness of less than 30 nm.

7. A method of forming dual interconnects in manufacturing a magnetoresistive memory cell, the method comprising:

providing an intermediate product comprising: a semiconductor substrate including active structures on a surface thereof; at least one metallization layer comprising a plurality of metallic lines disposed above the active structures of the semiconductor substrate; a first non-conductive layer comprising a non-conductive material disposed above the metallization layer and including a via contact for conductively contacting a first one of the metallic lines; a magnetoresistive junction element disposed above the first non-conductive layer and conductively connected to the via contact; a metallic hard mask disposed on the magnetoresistive junction element and conductively connected therewith; a second non-conductive layer comprising a non-conductive material disposed above the first non-conductive layer at least in a region over the hard mask and at least in a region over a second one of the metallic lines of the metallization layer; a third non-conductive layer comprising a non-conductive material having etch-selectivity as to the second non-conductive layer disposed at least in a region above the hard mask; and a fourth non-conductive layer disposed at least on the third non-conductive layer;

fully opening the first trench to uncover the hard mask;

fully opening the second trench to uncover the second metallic line;

filling the first trench with conductive material;

filling the second trench with conductive material; and

performing a cleaning operation using the third non-conductive layer as a protection layer.

8. A method of forming dual interconnects in manufacturing a magnetoresistive memory cell, the method comprising:

providing an intermediate product comprising: a semiconductor substrate including active structures on a surface thereof; at least one metallization layer comprising a plurality of metallic lines disposed above the active structures of the semiconductor substrate; a first non-conductive layer comprising a non-conductive material disposed above the metallization layer and including a via contact for conductively contacting a first one of the metallic lines; a magnetoresistive junction element disposed above the first non-conductive layer and conductively connected to the via contact; a metallic hard mask disposed on the magnetoresistive junction element and conductively connected therewith, the hard mask comprising a thickness of less than 30 nm; a second non-conductive layer comprising a non-conductive material disposed above the first non-conductive layer at least in a region over the hard mask and at least in a region over a second one of the metallic lines of the metallization layer; a third non-conductive layer comprising a non-conductive material having etch-selectivity as to the second non-conductive layer disposed at least in a region above the hard mask; and a fourth non-conductive layer disposed at least on the third non-conductive layer;

fully opening the first trench to uncover the hard mask;

fully opening the second trench to uncover the second metallic line;

filling the first trench with conductive material; and

filling the second trench with conductive material.