Semiconductor device and method of controlling said semiconductor device
View Patent ↗A semiconductor device includes: memory blocks each having groups of memory cells that are connected to word lines; select gates for selecting the groups of memory cells; and an apply circuit that applies, at the time of reading data, a back bias to the select gates of unselected memory blocks.
1. A semiconductor device comprising:
memory blocks each having groups of memory cells that are connected to word lines;
select gates for selecting the groups of memory cells; and
an apply circuit that applies, at the time of reading data, a back bias to the select gates of unselected memory blocks.
2. The semiconductor device as claimed in claim 1 , wherein each select gate comprises a storage element.
3. The semiconductor device as claimed in claim 2 , wherein each select gate is in a programmed state.
4. The semiconductor device as claimed in claim 1 , further comprising select lines that are respectively connected to the select gates,
wherein each select line is spaced apart from an adjacent one of the word lines at a pitch at which the word lines are arranged.
5. The semiconductor device as claimed in claim 1 , further comprising select lines that are respectively connected to the select gates,
wherein each select line has a width substantially equal to the width of each word line.
6. The semiconductor device as claimed in claim 1 , wherein the memory cells are of a floating gate type.
7. The semiconductor device as claimed in claim 1 , wherein the memory cells are of a SONOS type.
8. The semiconductor device as claimed in claim 1 , wherein the select gates comprise the same type of transistors as that of the memory cells.
9. The semiconductor device as claimed in claim 1 , wherein the select gates comprise floating gate type memory cells.
10. The semiconductor device as claimed in claim 1 , wherein the select gates comprise SONGS type memory cells.
11. The semiconductor device as claimed in claim 1 , wherein the select gates are select drain gates.
12. The semiconductor device as claimed in claim 1 , wherein the memory cells of each of the groups are connected in series and coupled to a corresponding one of the word lines.
13. A method of controlling a semiconductor device including memory blocks each having groups of memory cells connected to word lines, and select gates that select the groups of memory cells,
the method comprising the steps of:
selecting one of the memory blocks at the time of reading data; and
applying a back bias to the select gates of unselected memory blocks.
14. The method as claimed in claim 13 , wherein the select gates comprise storage elements.
15. A method of controlling a semiconductor device, comprising the steps of:
precharging, at the time of reading data, a bit line running in memory blocks each having groups of memory cells connected to word lines, and select gates that select the groups of memory cells; and
applying a back bias to the select gates of unselected blocks in a sensing period that follows a precharging period.
16. The method as claimed in claim 15 , further comprising the steps of:
erasing the memory cells of a selected block; and
programming the select gates in the selected block having erased memory cells.