Circuit for generating ternary signal
View Patent ↗A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each source terminal thereof is respectively connected to the three power supplies, and a sequential circuit that outputs control signals controlling the transistors. The sequential circuit outputs control signals that make the first and the third transistors be switched in a complementary manner in an initial state, and make the second and the third transistors be switched in a state that it is released from the initial state.
1. A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal from an output terminal, the circuit for generating a ternary signal comprising:
a first transistor being on-off controlled by a first control signal, wherein a source is connected to a high-potential-side power supply and a drain is connected to the output terminal;
a second transistor being on-off controlled by a second control signal, wherein a source is connected to a first low-potential-side power supply and a drain is connected to the output terminal;
a third transistor being on-off controlled by a third control signal, wherein a source is connected to a second low-potential-side power supply that is lower than the first low-potential-side power supply and a drain is connected to the output terminal; and
a sequential circuit receiving the input-control signal and the reset signal, being set to an initial state when the reset signal is a first signal level, outputting the first control signal and the third control signal that make the first transistor and the third transistor be switched in a complementary manner in compliance with a level of the input-control signal in the initial state, being released from the initial state when the reset signal is switched from the first signal level to a second signal level, and outputting the second control signal and the third control signal that make the second transistor and the third transistor be switched in a complementary manner in compliance with a level of the input-control signal after a falling edge of the input-control signal is detected in a state that the sequential circuit is released from the initial state.
2. The circuit for generating a ternary signal of claim 1 ,
wherein the sequential circuit includes
an edge detecting circuit having an inverter for inverting the input-control signal and outputting the inverted signal as the third control signal, and a D-type flip-flop circuit for outputting an output control signal being high when a rising edge of the third control signal is detected in a state that the reset signal is low and being low when the reset signal is high; and
a switching circuit outputting the first control signal and the second control signal in compliance with the output control signal and the input-control signal.
3. The circuit for generating a ternary signal of claim 2 ,
wherein the switching circuit includes:
an NAND circuit for inverting a logical sum of a inverted signal of the output control signal and the input-control signal and outputting the inverted signal as the first control signal, and an AND circuit for outputting a logical sum of the output control signal and the input control signal as the second control signal, and wherein
the first transistor is a P-channel MOS transistor,
the second transistor is a first N-channel MOS transistor,
the third transistor is a second N-channel MOS transistor,
the high-potential-side power supply is a positive potential,
the first low-potential-side power supply is a zero potential, and
the second low-potential-side power supply is a negative potential.
4. The circuit for generating a ternary signal of claim 3 , further comprising:
a first level-shifting circuit that is provided between an output terminal of the inverter and a gate of the third transistor, and shifts a voltage level of a signal inputted thereto in compliance with the signal.
5. The circuit for generating a ternary signal of claim 3 , further comprising:
a first level-shifting circuit that is provided between an output terminal of the inverter and a gate of the third transistor, and shifts a voltage level of a signal inputted thereto in compliance with the signal, and
a second level-shifting circuit that is provided between an output terminal of the NAND circuit and a gate of the first transistor, and shifts a voltage level of a signal inputted thereto in compliance with the signal.
6. The circuit for generating a ternary signal of claim 2 ,
wherein the switching circuit includes:
a first NAND circuit for inverting a logical sum of a inverted signal of the output control signal and the input-control signal and outputting the inverted signal as the first control signal, and a second NAND circuit for inverting a logical sum of the output control signal and the input-control signal and outputting the inverted signal as the second control signal, and wherein
the first transistor is a first P-channel MOS transistor,
the second transistor is a second P-channel MOS transistor,
the third transistor is a N-channel MOS transistor,
the high-potential-side power supply is a first positive potential,
the first low-potential-side power supply is a second positive potential, and
the second low-potential-side power supply is a zero potential.
7. The circuit for generating a ternary signal of claim 6 , further comprising:
a rectifier provided between the first low-potential-side power supply and a source of the second transistor.
8. The circuit for generating a ternary signal of claim 6 , further comprising:
a first level-shifting circuit that is provided between an output terminal of the first NAND circuit and a gate of the first transistor, and shifts a voltage level of a signal inputted thereto in compliance with the signal, and
a second level-shifting circuit that is provided between an output terminal of the second NAND circuit and a gate of the second transistor, and shifts a voltage level of a signal inputted thereto in compliance with the signal.
9. The circuit for generating a ternary signal of claim 7 , further comprising:
a first level-shifting circuit that is provided between an output terminal of the first NAND circuit and a gate of the first transistor, and shifts a voltage level of a signal inputted thereto in compliance with the signal, and
a second level-shifting circuit that is provided between an output terminal of the second NAND circuit and a gate of the second transistor, and shifts a voltage level of a signal inputted thereto in compliance with the signal.