Backside imaging through a doped layer
View Patent ↗Backthinning in an area selective manner is applied to CMOS imaging sensors 12 for use in electron bombarded active pixel array devices. A further arrangement results in an array of collimators 51 aligned with pixels 42 or groups of pixels of an active pixel array providing improved image contrast of such image sensor. Provision of a thin P-doped layer 52 on the illuminated rear surface provides both a diffusion barrier resulting in improved resolution and a functional shield for reference pixels. A gradient in concentration of P-doped layer 52 optimizes electron collection at the pixel array.
1. The method of sensing an image projected on the rear surface of a back illuminated semiconductor pixel array, comprising
forming a P-doped layer of selected thickness on said rear surface to achieve a desired conductivity therein, whereby a conduction band potential barrier is created, said P-doped layer incorporating a doping ramp to accelerate electrons toward said semiconductor pixel array,
preparing a flux distribution of electrons corresponding to said image,
accelerating said electrons of said flux distribution to a selected energy,
intercepting said electrons on said P-doped layer of semiconductor,
generating within said P-doped layer a plurality of electron-hole pairs for each said selected energy electron,
collecting said generated electrons at pixels correspondingly proximate each said generated electron-hole pair, whereby said pixel array contains information comprising said image.
2. The method of claim 1 wherein said step of forming comprises varying the conductivity of said P-doped layer within the thickness of said P-doped layer.
3. The method of claim 1 in which the surface doping concentration at the rear surface of the semiconductor pixel array on which an image is projected is doped at a level greater than or equal to 5×10 18 atoms per cubic centimeter with the concentration dropping to less than 10 18 within the first micron of the surface.
4. The method of claim 1 in which said semiconductor array comprises a CMOS sensor.
5. The method of claim 1 in which said semiconductor array comprises a CCD sensor.
6. The method of claim 1 in which said semiconductor array comprises a photodiode array.
7. The method of claim 1 in which said P-doped layer is manufactured by being overlaid with a multiple stop layer structure comprising an I-P-I epitaxial structure.