Granted Patent B2

US 7,649,932 · App. 11/291,344 · Granted Jan 19, 2010

Abstract

Claims (84)

1. A segmented equalizer comprising:

a plurality of feedforward equalizer segments, each feedforward equalizer segment responsive to delayed samples of an input signal {v n }, wherein n is an index of samples, and including a filter block for filtering the delayed samples by using coefficients which are updated based on a step size generated for each equalizer segment, each feedforward equalizer segment including a shift block coupled to receive input from the filter block and an exponent control block coupled to a coefficient update block and a step size control block for generating a step size, a different step size being generated for each segment;

a first feedforward summer associated with the last equalizer segment;

a decision block; and

a second summer, the decision block coupled to receive the output of the first feedforward summer and operative to generate an equalizer output {d n }, the second summer operative to subtract the output of the first feedforward summer from the equalizer output {d n } to generate the error {e n },

wherein each of the feedforward equalizer segments is a block floating point feedforward equalizer segment including a delay line block for generating the delayed sample input by receiving sample inputs from a previous feedforward equalizer segment except a first feedforward equalizer segment, which receives input signal {v n } and provides the delayed samples to the filter block.

2. A segmented equalizer, as recited in claim 1 , wherein each of the filter blocks of each of the feedforward equalizer segments generates an output Y n,m defined by:

y

n

,

m

=

∑

l

=

0

L

-

1

⁢

v

n

-

i

,

m

⁢

c

i

,

m

′

wherein c′ i,m are coefficients for segment m and V n−i,m 's are the delayed input signals for segment m.

3. A segmented equalizer, as recited in claim 2 , wherein

The output Combination Equation, i.e. generation of y n , is:

y

n

=

∑

m

=

0

M

-

1

⁢

y

n

,

m

⁡

(

a

j

m

)

-

1

A Where c i,m ′=c i,m a j m , a is the base for the block floating point (BFP) operation, j m is the exponent part for segment m, a j m is the equivalent scaling for segment m, and its inverse (a j m ) −1 's are combination weighting in forming the equalizer output.

4. A segmented equalizer, as recited in claim 3 , wherein the coefficient update block of each segment of each stage performs a function implementing:

c′ i k+1 =c′ i k +Δ m a j m e n v

Where e n =d n −y n , Δ n is the step size.

5. A segmented equalizer, as recited in claim 1 , wherein the segmented equalizer is a segmented sparse equalizer.

6. A segmented equalizer, as recited in claim 5 , including a first switch coupled to the plurality of segments for selectively providing non-zero delayed samples.

7. A segmented equalizer, as recited in claim 1 , further including a plurality of feedforward summers including the first summer, each of which is associated with one of the equalizer segments and receives an output of a corresponding one of the plurality of feedforward equalizer segments and an output of a previous summer and adds the two outputs to generate a summer output for use by a next summer.

8. A segmented equalizer, as recited in claim 4 , wherein Δ m is set to

Δ c (a j m ) −1 , and the coefficient update block of each segment of each stage performs a function implementing:

c′ i,m k+1 =c′ i,m k +Δ c e n v n−i , i= 0 , . . . , L− 1 , m= 0 , . . . , M− 1.

9. A segmented equalizer, as recited in claim 8 , wherein Δ c is a power of a.

10. A segmented equalizer comprising:

a plurality of feedforward equalizer segments, each feedforward equalizer segment responsive to delayed samples of an input signal {v n }, wherein n is an index of samples, and including a filter block for filtering the delayed samples by using coefficients which are updated based on a step size generated for each equalizer segment, wherein each feedforward equalizer segment generates an output {y n,m }, each feedforward equalizer segment including a shift block coupled to receive input from the filter block and an exponent control block coupled to a coefficient update block and a step size control block for generating a step size, a different step size being generated for each segment;

a first summer, coupled to receive the plurality of feedforward equalizer segment outputs {y n,m } and generate an equalizer filter output {y n };

a decision block; and

a second summer, the decision block coupled to receive the equalizer filter output {y n } and generate an equalizer output {d n }, the second summer operative to subtract the equalizer filter output {y n } from the equalizer output {d n } to generate an error {e n }, wherein each of the feedforward equalizer segments is a block floating point feedforward equalizer segment including a delay line block for generating the delayed sample input by receiving sample inputs from a previous feedforward equalizer segment except a first feedforward equalizer segment which receives input signal {v n } and providing the delayed samples to the filter block.

11. A segmented equalizer, as recited in claim 10 , wherein the segmented equalizer is a segmented sparse equalizer.

12. A segmented equalizer, as recited in claim 11 , including a first switch coupled to the plurality of segments for selectively providing non-zero delayed samples.

13. A segmented equalizer comprising:

a plurality of feedback equalizer segments, each feedback equalizer segment responsive to delayed equalizer decisions {d n }, wherein n is an index of decisions, and including a filter block for filtering the delayed decisions by using coefficients which are updated based on a step size generated for each feedback equalizer segment, wherein each feedback equalizer segment generates an output {x n,1 }, each feedback equalizer segment including a shift block coupled to receive input from the filter block and an exponent control block coupled to a coefficient update block and a step size control block for generating a step size, a different step size being generated for each segment;

a first summer, coupled to receive the plurality of feedback equalizer segment outputs {x n,1 } and generate an equalizer filter output {y n };

a decision block; and

a second summer, the decision block coupled to receive the equalizer filter output {y n } and generate delayed equalizer decisions {d n }, the second summer operative to subtract the equalizer filter output {y n } from delayed equalizer decisions {d n } to generate the error {e n },

wherein each of the feedback equalizer segments is a block floating point feedback equalizer segment including a delay line block for generating the delayed decisions by receiving decisions from a previous feedback equalizer segment except a first feedback equalizer segment which receives delayed equalizer decisions {d n }, and providing the delayed decisions to the filter block.

14. A segmented equalizer, as recited in claim 13 , wherein the segmented equalizer is a segmented sparse equalizer.

15. A segmented equalizer, as recited in claim 14 , including a first switch coupled to the plurality of segments for selectively providing non-zero delayed samples.

Assignments (14)