Semiconductor device and electronic instrument
A semiconductor device including: a DRAM which is a volatile memory; a PLL circuit which outputs an operation clock signal generated by multiplying an input clock signal; a circuit block which operates in synchronization with the operation clock signal; first and second refresh controllers for requesting a refresh operation of the DRAM; and a memory controller which arbitrates between an access request for the DRAM from the circuit block and a refresh request from the first refresh controller. In a first mode in which the PLL circuit operates, the first refresh controller issues the refresh request to the DRAM controller. In a second mode in which the operation of the PLL circuit stops, the second refresh controller issues the refresh request, the refresh request bypassing the DRAM controller.
1. A semiconductor device, comprising:
a volatile memory which retains data by a cyclic refresh operation;
a first PLL circuit which multiplies an input clock signal and outputs an operation clock signal having a frequency higher than a frequency of the input clock signal;
a circuit block which operates in synchronization with the operation clock signal;
first and second refresh controllers for requesting the refresh operation of the volatile memory; and
a memory controller which arbitrates between an access request for the volatile memory from the circuit block and a refresh request from the first refresh controller, and controls access to the volatile memory in response to one of the access request and the refresh request,
wherein, in a first mode in which the first PLL circuit operates, the first refresh controller operates in synchronization with the operation clock signal and issues the refresh request for the volatile memory to the memory controller; and
wherein, in a second mode in which the first PLL circuit stops operation, supply of the operation clock signal to the first refresh controller and the memory controller is stopped, and the second refresh controller operates in synchronization with the input clock signal and issues the refresh request to the volatile memory, the refresh request bypassing the memory controller.
2. The semiconductor device as defined in claim 1 , further comprising:
a second PLL circuit which has a multiplication factor lower than a multiplication factor of the first PLL circuit, multiplies the input clock signal, and outputs a refresh clock signal having a frequency higher than the frequency of the input clock signal and lower than the frequency of the operation clock signal,
wherein, in the second mode, the second refresh controller operates in synchronization with the refresh clock signal and issues the refresh request to the volatile memory, the refresh request bypassing the memory controller.
3. The semiconductor device as defined in claim 1 , further comprising:
a register for setting control information which indicates a refresh target block when a storage region of the volatile memory is divided into a plurality of blocks,
wherein the refresh operation is performed for only the refresh target block of the volatile memory indicated by the control information in response to the refresh request from the second refresh controller.
4. The semiconductor device as defined in claim 1 , further comprising:
a first PLL circuit operation control register which causes the first PLL circuit to start to operate, and is accessed asynchronously to the operation clock signal and the input clock signal,
wherein the first PLL circuit starts on condition that the first PLL circuit operation control register has been accessed in the second mode.
5. The semiconductor device as defined in claim 1 ,
wherein the volatile memory retains image data supplied to a display driver which drives a display panel.
6. An electronic instrument, comprising:
a display panel;
a display driver which drives the display panel based on image data; and
the semiconductor device as defined in claim 5 which supplies data retained in the volatile memory to the display driver as the image data.
7. An electronic instrument, comprising:
the semiconductor device as defined in claim 1 .
8. A semiconductor device, comprising:
a volatile memory which retains data by a cyclic refresh operation;
a first PLL circuit which multiplies an input clock signal and outputs an operation clock signal having a frequency higher than a frequency of the input clock signal;
a circuit block which operates in synchronization with the operation clock signal;
a refresh controller for requesting the refresh operation of the volatile memory; and
a memory controller which arbitrates between an access request for the volatile memory from the circuit block and a refresh request from the refresh controller, and controls access to the volatile memory in response to one of the access request and the refresh request,
wherein, in a first mode in which the first PLL circuit operates, the refresh controller operates in synchronization with the operation clock signal and issues the refresh request for the volatile memory; and
wherein, in a second mode in which the first PLL circuit stops operation, the refresh controller operates in synchronization with the input clock signal and issues the refresh request for the volatile memory.
9. The semiconductor device as defined in claim 8 , further comprising:
a second PLL circuit which has a multiplication factor lower than a multiplication factor of the first PLL circuit, multiplies the input clock signal, and outputs a refresh clock signal having a frequency higher than the frequency of the input clock signal and lower than the frequency of the operation clock signal,
wherein, in the second mode, the refresh controller operates in synchronization with the refresh clock signal and issues the refresh request to the volatile memory, the refresh request bypassing the memory controller.
10. The semiconductor device as defined in claim 8 , further comprising:
a register for setting control information which indicates a refresh target block when a storage region of the volatile memory is divided into a plurality of blocks,
wherein the refresh operation is performed for only the refresh target block of the volatile memory indicated by the control information in response to the refresh request from the memory controller.
11. The semiconductor device as defined in claim 8 , further comprising:
a first PLL circuit operation control register which causes the first PLL circuit to start to operate, and is accessed asynchronously to the operation clock signal and the input clock signal,
wherein the first PLL circuit starts on condition that the first PLL circuit operation control register has been accessed in the second mode.
12. The semiconductor device as defined in claim 8 ,
wherein the volatile memory retains image data supplied to a display driver which drives a display panel.
13. An electronic instrument, comprising:
a display panel;
a display driver which drives the display panel based on image data; and
the semiconductor device as defined in claim 12 which supplies data retained in the volatile memory to the display driver as the image data.
14. An electronic instrument, comprising:
the semiconductor device as defined in claim 8 .