Thin film transistor array substrate and fabricating method thereof
A thin film transistor array substrate and a fabricating method are disclosed. A gate line and a data line cross each other and a thin film transistor (TFT) is provided at the intersection between the gate and data lines. A protective film covers the data line and the thin film transistor and has a contact hole exposing a drain electrode of the TFT. A pixel electrode is connected, via the contact hole, to the drain electrode of the TFT. A storage capacitor includes a gate insulating film between the pixel electrode and the gate line and/or a common line. Some or all of the protective film within the storage capacitor is removed such that the storage capacitor contains no protective film or a layer of protective film that is thinner than the portion covering the TFT.
1 . A thin film transistor array substrate comprising:
a gate line and a data line crossing each other on a substrate;
a thin film transistor provided at an intersection between the gate line and the data line;
a storage capacitor including at least one of another gate line or a common line separated from the gate line;
a protective film that covers the data line and the thin film transistor and the at least one of the other gate line or the common line in the storage capacitor, the protective film in the storage capacitor thinner than the protective film that covers the data line and the thin film transistor, the protective film having a contact hole exposing a drain electrode of the thin film transistor;
a pixel electrode connected, via the contact hole, to the drain electrode of the thin film transistor, the pixel electrode forming one electrode of the storage capacitor.
2 . The thin film transistor array substrate as claimed in claim 1 , further comprising a gate insulating film disposed between the gate line and a semiconductor of the thin film transistor.
3 . The thin film transistor array substrate as claimed in claim 2 , wherein the gate insulating film is disposed in the storage capacitor.
4 . The thin film transistor array substrate as claimed in claim 3 , wherein, of the gate insulating film and the protective film, only the gate insulating film is disposed in the storage capacitor.
5 . The thin film transistor array substrate as claimed in claim 4 , wherein, in the storage capacitor, the pixel electrode contacts the gate insulating film and the gate insulating film contacts the gate electrode.
6 . The thin film transistor array substrate as claimed in claim 3 , wherein both the gate insulating film and the protective film are disposed in the storage capacitor.
7 . The thin film transistor array substrate as claimed in claim 6 , wherein, in the storage capacitor, the pixel electrode contacts the protective film and the gate insulating film contacts the gate electrode.
8 . The thin film transistor array substrate as claimed in claim 1 , wherein the common line crosses the pixel electrode.
9 . The thin film transistor array substrate as claimed in claim 1 , wherein, of the common line and the other gate line, only the common line forms the storage capacitor.
10 . The thin film transistor array substrate as claimed in claim 1 , wherein the substrate is a transparent substrate.
11 . A method of fabricating a thin film transistor array substrate, the method comprising:
forming a gate line and at least one of a common line and another gate line separated from the gate line on a substrate;
forming a data line crossing the gate line and a thin film transistor provided at the intersection between the gate line and the data line;
forming a protective film covering the thin film transistor;
removing a portion of the protective film to form a contact hole exposing a drain electrode of the thin film transistor and at least thin the protective film in a storage capacitor area; and
forming a pixel electrode connected, via the contact hole, to the drain electrode of the thin film transistor, a storage capacitor being formed that includes the pixel electrode and the at least one of the common line or the other gate line.
12 . The method of fabricating the thin film transistor array substrate as claimed in claim 11 , further comprising forming a gate insulating film that covers at least one of the common line and the other gate line.
13 . The method of fabricating the thin film transistor array substrate as claimed in claim 12 , wherein removing the portion of the protective film comprises:
aligning a diffractive mask on the protective film;
forming a photo-resist pattern having a relatively low height at the storage capacitor area using the diffractive mask;
patterning the protective film using the photo-resist pattern as a mask to define the contact hole;
ashing the photo-resist pattern to expose the protective film in the storage capacitor area;
at least partially removing the exposed protective film using the ashed photo-resist pattern as a mask; and
removing the ashed photo-resist pattern.
14 . The method of fabricating the thin film transistor array substrate as claimed in claim 13 , wherein at least partially removing the exposed protective film comprises adjusting an etching time while etching the exposed protective film to adjust a height of the exposed protective film.
15 . The method of fabricating the thin film transistor array substrate as claimed in claim 11 , wherein removing the portion of the protective film comprises completely removing the protective film in the storage capacitor area.
16 . The method of fabricating the thin film transistor array substrate as claimed in claim 11 , wherein the protective film covering the thin film transistor is not substantially thinned during removal of the portion of the protective film.
17 . The method of fabricating the thin film transistor array substrate as claimed in claim 11 , wherein the common line crosses the pixel electrode.
18 . The method of fabricating thin film transistor array substrate as claimed in claim 11 , further comprising forming a gate insulating film in the storage capacitor.
19 . The method of fabricating thin film transistor array substrate as claimed in claim 18 , wherein, of the gate insulating film and the protective film, only the gate insulating film is disposed in the storage capacitor.
20 . The method of fabricating thin film transistor array substrate as claimed in claim 19 , wherein, in the storage capacitor, the pixel electrode contacts the gate insulating film and the gate insulating film contacts the gate electrode.
21 . The method of fabricating thin film transistor array substrate as claimed in claim 18 , wherein both the gate insulating film and the protective film are disposed in the storage capacitor.
22 . The method of fabricating thin film transistor array substrate as claimed in claim 21 , wherein, in the storage capacitor, the pixel electrode contacts the protective film and the gate insulating film contacts the gate electrode.
23 . The method of fabricating thin film transistor array substrate as claimed in claim 11 , wherein, of the common line and the other gate line, only the common line forms the storage capacitor.
24 . The method of fabricating thin film transistor array substrate as claimed in claim 11 , wherein the substrate is a transparent substrate.
25 . A liquid crystal display comprising:
a thin film transistor array substrate that includes:
a first gate line and a data line crossing each other on a transparent substrate;
a thin film transistor provided at an intersection of the first gate line and the data line;
a protective film that covers the data line and the thin film transistor;
a gate insulating film that covers the first gate line; and
a pixel electrode connected to a drain electrode of the thin film transistor, the pixel electrode separated from a conductive material by an insulator to form a storage capacitor in a storage capacitor area, the insulator including at least one of the protective film or the gate insulating film, a thickness of the insulator in the storage capacitor area being thinner than a combined thickness of the protective film and the gate insulating film outside the storage capacitor area;
a transparent substrate opposing the thin film transistor array substrate; and
liquid crystal disposed between the substrates.
26 . The liquid crystal display as claimed in claim 25 , wherein the protective film in the storage capacitor area is thinner than the protective film outside the storage capacitor area and the gate insulating film in the storage capacitor area has the same thickness as the gate insulating film outside the storage capacitor area.
27 . The liquid crystal display as claimed in claim 26 , wherein the insulator comprises only the gate insulating film in the storage capacitor area.
28 . The liquid crystal display as claimed in claim 26 , wherein the insulator comprises both the gate insulating film and the protective film in the storage capacitor area.
29 . The liquid crystal display as claimed in claim 25 , wherein the conductive material comprises a common line.
30 . The liquid crystal display as claimed in claim 25 , wherein the conductive material comprises a second gate line adjacent to the first gate line.