Liquid crystal display and driving method thereof
View Patent ↗A liquid crystal display device includes a first transistor that outputs a charge share voltage to a data line in response to a first output control signal. A second transistor outputs a pre-charge voltage, which is greater than the charge share voltage, to the data line in response to a second output control signal which is delayed in phase from the first output control signal. A third transistor outputs a data voltage to the data line in response to at least one of the first and second output control signals. A logic circuit controls the transistors in response to the output control signals and a polarity control signal that controls the polarity of the data voltage.
1. A liquid crystal display device, comprising:
a first transistor that outputs a charge share voltage to a data line in response to a first output control signal;
a logic circuit that outputs first to third output signals in response to the first output control signal, a second output control signal and a polarity control signal, wherein the second output control signal is phase-shifted from the first output control signal and the polarity control signal controls a polarity of a data signal;
a second transistor that outputs a positive pre-charge voltage, which is greater than the charge share voltage, to the data line in response to the first output signal;
a third transistor that outputs a negative pre-charge voltage, which is lower than the charge share voltage, the data line in response to the second output signal; and
a fourth transistor that outputs the data voltage to the data line in response to the third output signal.
2. The liquid crystal display device according to claim 1 , wherein the first transistor includes:
a first n-type transistor which is controlled by the first source output signal,
wherein the second transistor includes:
a second n-type transistor that outputs the positive pre-charge voltage to the data line in response to the first output signal when the polarity of the data voltage is positive;
wherein the third transistor includes:
a third n-type transistor that outputs the negative pre-charge voltage to the data line in response to the second output signal when the polarity of the data voltage is negative; and
wherein the fourth transistor includes:
a fourth p-type transistor that outputs the data voltage to the data line in response to the third output signal.
3. The liquid crystal display device according to claim 2 , wherein the logic circuit includes:
an OR gate that controls the fourth p-type transistor by performing a logic OR operation on the first and second output control signals;
a first AND gate that controls the second n-type transistor by performing a logic AND operation on the second output control signal and the polarity control signal; and
a second AND gate that controls the third n-type transistor by performing a logic AND operation on the second output control signal and a inverted polarity control signal, wherein the inverted polarity control signal is inverted from the polarity control signal.
4. The liquid crystal display device according to claim 1 , wherein the second source output signal is shifted by one pulse width of the first output signal.
5. The liquid crystal display device according to claim 1 , wherein the first and second output control signals are periodically generated every one horizontal period.
6. The liquid crystal display device according to claim 1 , wherein the polarity control signal has a logic value inverted for each one horizontal period to control the polarity of the data voltage supplied to the data lines of the liquid crystal display panel.
7. The liquid crystal display device according to claim 1 , wherein the output control signals and the polarity control signal are generated by a timing controller.
8. A liquid crystal display device, comprising:
a first n-type transistor which is controlled by a first output control signal and outputs a charge share voltage to a data line in response to the first output control signal;
a first AND pate that outputs a first output signal by performing a logic AND operation on a second output control signal and a polarity control signal, wherein the second output control signal is phase-shifted from the first output control signal and the polarity control signal controls a polarity of a data signal;
a second n-type transistor that outputs a positive pre-charge voltage, which is greater than the charge share voltage, to the data line in response to the first output signal when a polarity of a data voltage is positive;
a second AND gate that outputs a second output signal by performing a logic AND operation on the second output control signal and a inverted polarity control signal, wherein the inverted polarity control signal is inverted from the polarity control signal;
a third n-type transistor that outputs a negative pre-charge voltage, which is lower than the charge share voltage, to the data line in response to the second output signal when the polarity of the data voltage is negative;
an OR gate that outputs a third output signal by performing a logic OR operation on the first and second output control signals; and
a p-type transistor that supplies the data voltage to the data line of a liquid crystal display panel in response to the third output signal.
9. A method for driving a liquid crystal display device, the method comprising:
supplying a charge share voltage to a data line in response to a first output control signal;
outputting a first output signal by performing a logic AND operation on a second output control signal and a polarity control signal, wherein the second output control signal is phase-shifted from the first output control signal and the polarity control signal controls a polarity of a data signal;
supplying a positive pre-charge voltage, which is greater than the charge share voltage, to the data line in response to the first output signal when a polarity of a data voltage is positive;
outputting a second output signal by performing a logic OR operation on the first and second output control signals;
supplying the data voltage to the data line in response to the second output signal;
outputting a third output signal by performing a logic AND operation on the second output control signal and a inverted polarity control signal, wherein the inverted polarity control signal is inverted from the polarity control signal; and
supplying a negative pre-charge voltage, which is lower than the charge share voltage, to the data line in response to the third output signal when the polarity of the data voltage is negative.
10. The method of claim 9 , wherein the charge share voltage is supplied via a first transistor.
11. The method of claim 9 , wherein the positive pre-charge share voltage is supplied via a second transistor.
12. The method of claim 9 , wherein the data voltage is supplied via a third transistor.
13. The method of claim 9 , wherein the negative pre-charge share voltage is supplied via a fourth transistor.