Signal line for display device and thin film transistor array panel including the signal line
View Patent ↗A thin film transistor (TFT) array panel with signal lines that have low resistivity is presented. The TFT array panel includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode facing the source electrode with a gap, and a pixel electrode connected to the drain electrode. In one embodiment, at least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a Mo-containing conductor, a second conductive layer made of a Cu-containing conductor, and a third conductive layer made of a MoN-containing conductor.
1. A signal line comprising:
a first conductive layer made of a Mo-containing conductor;
a second conductive layer of a Cu-containing conductor; and
a third conductive layer made of a MoN-containing conductor,
wherein the second conductive layer is disposed on the first conductive layer, and the third conductive layer is disposed on the second conductive layer.
2. The signal line of claim 1 , wherein the signal line is a gate line or a data line of a thin film transistor array panel.
3. The signal line of claim 1 , wherein the second conductive layer is made of pure Cu or a Cu-alloy.
4. The signal line of claim 1 , wherein the first conductive layer has a thickness of 50 to 500 Å, the second conductive layer has a thickness of 1000 to 3000 Å, and the third conductive layer has a thickness of 50 to 2000 Å.
5. The signal line of claim 1 , wherein the signal line has tapered edges, and the inclination angles of the edges are about 30-80 degrees.
6. A thin film transistor array panel comprising:
an insulating substrate;
a gate line formed on the insulating substrate;
a gate insulating layer formed on the gate line;
a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being separated from the source electrode; and
a pixel electrode connected to the drain electrode, wherein the gate line and the data line and drain electrode include a first conductive layer made of a Mo-containing conductor, a second conductive layer made of a Cu-containing conductor, and a third conductive layer made of a MoN-containing conductor, wherein the second conductive layer is disposed on the first conductive layer, and the third conductive layer is disposed on the second conductive layer.
7. The thin film transistor array panel of claim 6 , wherein the first conductive layer has a thickness of 50 to 500 Å, the second conductive layer has a thickness of 1000 to 3000 Å, and the third conductive layer has a thickness of 50 to 2000 Å.
8. The thin film transistor array panel of claim 6 , wherein the gate line and the data line and drain electrode have tapered edges, and the inclination angles of the edges are about 30-80 degrees.