Systems for implementing high speed and high integration chips
View Patent ↗Disclosed are methods and systems for implementing various circuitry within a high speed, high frequency signal environment such as an integrated circuit. In one embodiment, an improved clock tree mechanism utilizes multiple low power drivers to distribute a clock signal to various load cells. In another embodiment, a single circuitry in current mode logic is used to implement a combined multiplexer, buffer and level shifter. In other embodiments, improved static and partially static flip-flop circuitry is disclosed which uses fewer devices and less power than conventional circuitry while achieving the same functionality.
1. An apparatus for holding and releasing a data signal and a scan data signal, comprising:
a feed forward mechanism accepting said data signal;
a selection and transmission mechanism for selecting and transmitting one of said data signal and scan data signal;
a first latch configured to accept and hold said transmitted one of said data signal and said scan data signal;
a first driver, the input of said first driver coupled to the first latch and to said feed forward mechanism;
a transmission gate coupled to the output of said first driver;
a second latch coupled to the output of said transmission gate; and
an output diver coupled to the output of said second latch.
2. An apparatus according to claim 1 wherein said feed forward mechanism consists of two series connected transistors.
3. An apparatus according to claim 2 wherein said transistors are CMOS.
4. An apparatus according to claim 1 wherein said selection and transmission mechanism includes a first mechanism for said data signal and a second mechanism for said scan data signal.
5. An apparatus according to claim 4 wherein each said first and second mechanism consist of a inverter and series coupled transistor.
6. An apparatus according to claim 5 wherein a selection signal enables conduction either of the data signal through the inverter of the first mechanism or of the scan data signal through the inverter of the second mechanism.
7. An apparatus according to claim 1 wherein said first and second latches include a feedback path.
8. An apparatus according to claim 7 wherein said feedback path is configured as a large gate NMOS.
9. An apparatus according to claim 7 wherein said first and second latches include an inverter coupled to said feedback path.
10. An apparatus according to claim 1 wherein said first driver and said output driver are inverters.
11. An apparatus according to claim 2 wherein said feed forward mechanism further includes an inverter coupled to the first of the series connected transistors.
12. An apparatus for holding and releasing a data signal and a scan data signal, comprising:
a feed forward mechanism accepting said data signal;
a selection and transmission mechanism for selecting and transmitting one of said data signal and scan data signal;
a first latch configured to accept and hold said transmitted one of said data signal and said scan data signal;
a first driver, the input of said first driver coupled to the first latch and to said feed forward mechanism;
a transmission gate coupled to the output of said first driver; and
an output diver coupled to the output of said second latch.
13. An apparatus according to claim 12 wherein said feed forward mechanism consists of two series connected transistors.
14. An apparatus according to claim 13 wherein said transistors are CMOS.
15. An apparatus according to claim 12 wherein said selection and transmission mechanism includes a first mechanism for said data signal and a second mechanism for said scan data signal.
16. An apparatus according to claim 15 wherein each said first and second mechanism consist of a inverter and series coupled transistor.
17. An apparatus according to claim 16 wherein a selection signal enables conduction either of the data signal through the inverter of the first mechanism or of the scan data signal through the inverter of the second mechanism.
18. An apparatus according to claim 12 wherein said first and second latches include a feedback path.
19. An apparatus according to claim 18 wherein said feedback path is configured as a large gate NMOS.
20. An apparatus according to claim 18 wherein said first and second latches include an inverter coupled to said feedback path.
21. An apparatus according to claim 12 wherein said first driver and said output driver are inverters.
22. An apparatus according to claim 13 wherein said feed forward mechanism further includes an inverter coupled to the first of the series connected transistors.