Semiconductor devices and methods of manufacture thereof
View Patent ↗Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.
1. An intermediate state of a semiconductor device comprising:
a gate dielectric disposed over a workpiece;
a layer of conductive material comprising a thickness of about 30A° or less disposed over and in contact with the gate dielectric, the layer of conductive material comprising metal nitride;
a layer of semiconductive material disposed over and in contact with the 30A° thick layer of conductive material, the layer of semiconductive material and the layer of conductive material patterned to define a plurality of gate electrodes;
a p-type dopant implanted in the layer of semiconductor material of a portion of said plurality of gate electrodes to form p-channel semiconductor devices;
an n-type dopant implanted in the layer of semiconductor material of another portion of said plurality of gate electrodes to form n-channel semiconductor devices; and
a source region and a drain region formed in the workpiece proximate the gate dielectric.
2. The semiconductor device according to claim 1 , wherein the layer of conductive material comprises a thickness such that the layer of conductive material has a substantially negligible effect on a work function of the transistor.
3. The semiconductor device according to claim 1 , wherein the gate dielectric comprises a dielectric constant of about 3.9 to about 7.8.
4. The semiconductor device according to claim 1 , wherein the gate dielectric comprises an insulating material comprising Si combined with O, N, or both O and N.
5. The semiconductor device according to claim 1 , wherein the gate dielectic comprises a dielectric constant of about 4.0 or greater, and wherein the gate dielectric comprises HfO 2 , HfSiO x , Al 2 O 3 , ZrO 2 , ZrSiO x , Ta 2 O 5 , La 2 O 3 , SiO 2 , TiO 2 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST (Ba (a-x) Sr x TiO 3 ), PST (PbSc x Ta (1-a) O 3 ), nitrides thereof, Si x N y , SiON, HfAlO x , HfAlO x N 1-x-y , ZrAlO x , ZrAlO x N y , SiAlO x , SiAlO x N 1-x-y , HfSiAlO x , HfSiAlO x N y , ZrSiAlO x , ZrSiAlO x N y , PZN (PbZn x Nb (1-x) O 3 ), PZT (PbZr x Ti (1-x) O 3 ), PMN (PbMg x Nb (1-x) O 3 ), combinations thereof, or multiple layers thereof.
6. The semiconductor device according to claim 1 , wherein the semiconductor device comprises parts of CMOS devices.
7. The semiconductor device according to claim 6 , wherein the CMOS devices comprise semiconductor devices with symmetric threshold voltages.
8. The semiconductor device according to claim 1 , wherein the metal nitride is MoN.