Granted Patent B1

US 7,330,078 · App. 11/300,718 · Granted Feb 12, 2008

Abstract

Claims (76)

1. A method, comprising:

turning on a spread spectrum of an output reference signal in a phase-locked loop (PLL); and

limiting an overshoot in the output reference signal when turning on the spread spectrum, wherein limiting the overshoot comprises:

detecting an initial state of a spread address counter; and

loading a first counter of the PLL with a spread profile, the spread profile to cause an initial negative frequency slope in the output reference signal.

2. The method of claim 1 , wherein the output reference signal is a clock signal.

3. The method of claim 1 , wherein loading the first counter with the spread profile comprises:

loading a base value into the first counter after synchronously opening the PLL;

adding a first offset value of a plurality of offset values to the base value, the first offset value to decrease a frequency of the output reference signal;

loading the first added value into the first counter;

adding a second offset value of the plurality of offset values to the base value, the second offset value to decrease the frequency of the output reference signal; and

loading the second added value into the first counter after incrementing spread address counter.

4. The method of claim 3 , wherein the plurality of offset values substantially form an inverted triangular spread pattern in the output reference signal.

5. The method of claim 3 , wherein the plurality of offset values substantially form an inverted Lexmark spread pattern in the output reference signal.

6. The method of claim 1 , wherein limiting the overshoot comprises limiting the overshoot to be less than approximately 0.03% of the output reference signal.

7. The method of claim 1 , wherein limiting the overshoot comprises limiting the overshoot to achieve substantially no overshoot.

8. A method, comprising:

turning on a spread spectrum of an output reference signal in a phase-locked loop (PLL); and

limiting an undershoot in the output reference signal when turning on the spread spectrum, wherein limiting the undershoot comprises:

synchronously opening the PLL;

synchronously loading a first counter and a second counter of the PLL;

aligning a phase of an output signal of the first counter with a phase of an output signal of the second counter; and

synchronously closing the PLL and incrementing a spread address counter.

9. The method of claim 8 , wherein the output reference signal is a clock signal.

10. The method of claim 8 , wherein synchronously opening the PLL comprises:

detecting a spread enable signal from a serial interface;

sampling the spread enable signal by a reference clock signal at a first rising edge; and

activating a PFD control signal to open the PLL at a second falling edge of the reference clock signal.

11. The method of claim 10 , wherein synchronously loading the first counter and the second counter comprises:

activating a reset signal of the spread address counter at the second falling edge of the reference clock signal;

enabling spread gates in a spread ROM including a spread profile on a third rising edge of the reference clock signal; and

loading first base values into the first and second counters on the third rising edge of the reference clock signal.

12. The method of claim 11 , wherein aligning the phase of the output signal of the first counter with the phase of the output signal of the second counter comprises:

activating a reset signal of the first counter on the third rising edge of the reference clock signal;

activating a rest signal of the second counter on a third falling edge of the reference clock signal;

releasing the reset signal of the first counter on a fourth rising edge of the reference clock signal; and

releasing the reset signal of the second counter on a first rising edge of an overflow bit signal of the first counter.

13. The method of claim 12 , wherein synchronously closing the PLL and activating the spread address counter comprises:

deactivating the PFD control signal to close the PLL at a fourth falling edge of the reference clock signal;

releasing the reset signal of the spread address counter at the fourth falling edge of the reference clock; and

incrementing the spread address counter by 1 on a second rising edge of the overflow bit signal of the first counter.

14. The method of claim 8 , further comprising detecting an initial state of a spread address counter before synchronously opening the PLL.

15. The method of claim 8 , further comprising:

loading a base value into the first counter after synchronously opening the PLL;

adding a first offset value of a plurality of offset values to the base value, the first offset value to decrease a frequency of the output reference signal;

loading the first added value into the first counter;

adding a second offset value of the plurality of offset values to the base value, the second offset value to decrease the frequency of the output reference signal; and

loading the second added value into the first counter after incrementing spread address counter.

16. The method of claim 15 , wherein the plurality of offset values substantially form an inverted triangular spread pattern in the output reference signal.

17. The method of claim 15 , wherein the plurality of offset values substantially form an inverted Lexmark spread pattern in the output reference signal.

18. The method of claim 8 , wherein limiting the undershoot comprises limiting the undershoot to be less than approximately negative 0.03% of the output reference signal.

19. The method of claim 8 , wherein limiting the undershoot comprises limiting the undershoot to achieve substantially no undershoot.

20. An apparatus, comprising:

a phase-locked loop (PLL); and

a spread-control circuit coupled to the PLL, the spread spectrum switch to limit an overshoot and an undershoot in an output reference signal; wherein the spread-control circuit is configured to load a first counter of the PLL with a spread profile, the spread profile to cause an initial negative frequency slope in the output reference signal to limit the overshoot, wherein the spread-control circuit comprises:

a spread spectrum switch coupled to the PLL, the spread spectrum comprises a first, second, and third sampling flip-flops clocked by a crystal oscillator signal, the first, second, and third sampling flip-flops to sample an input spread spectrum enable signal, the first, second, and third sampling flip-flops configured to provide a plurality of control output signals;

a spread address counter coupled to the spread spectrum switch;

an adder to receive a first base value and a plurality of offset values of a spreading profile; and

a multiplexer coupled to an output of the adder, the multiplexer to receive the first base value and the added value from the adder.

21. The apparatus of claim 20 , wherein the PLL comprises:

a first counter coupled to the spread-control circuit, first counter to receive at least one of the first base value and the added value from the multiplexer;

a phase frequency detector and charge pump (PFD/CP) coupled to the first counter and the spread-control circuit;

a voltage control oscillator (VCO) coupled PFD/CP and the first counter, the VCO to generate an output reference signal; and

a second counter coupled to the PFD/CP and the spread-control circuit, the second counter to receive an input reference signal, wherein the input frequency is divided by a second base value of the second counter and multiplied by at least one of the first base value and the added value of the first counter.

22. The apparatus of claim 21 , further comprising:

a configuration read only memory (ROM) coupled to the second counter and the adder of the spread-control circuit, the configuration ROM comprises the first and second base values of the first and second counters; and

a spread ROM coupled to the adder of the spread-control circuit, the spread ROM comprises the plurality of offset values of the spreading profile.

23. The apparatus of claim 20 , wherein the plurality of control output signals comprise at least one of:

a phase frequency detector (PFD) control signal to open and close the PLL;

an address counter reset signal to activate and release the spread address counter;

a first counter reset signal to activate and release the first counter, the first counter to receive at least one of the base value and the added value from the multiplexer;

a second counter reset signal to activate and release the second counter, the second counter to receive the second base value; and

a divider control signal to load the first and second base values into the first and second counters.

24. The apparatus of claim 21 , further comprising:

a loop filter coupled to the PFD/CP and the VCO; and

a third counter coupled to the VCO, wherein the output frequency is divided by a value of the third counter to produce a clock frequency signal.

Assignments (9)