IP Library Granted Patent US 7,456,041
Granted Patent B2
US 7,456,041 · App. 11/301,032 · Granted Nov 25, 2008

Manufacturing method of a MEMS structure, a cantilever-type MEMS structure, and a sealed fluidic channel

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Quick Facts
Patent No.
US 7,456,041
App. No.
11/301,032
Granted
Nov 25, 2008
Kind
B2
Abstract

A method of manufacturing a MEMS structure including forming a porous layer having a predetermined thickness on the top surface of a substrate over an area where a cavity is to be formed; forming the cavity by etching the substrate below the porous layer; forming a membrane layer on the top surface to seal the cavity; and forming a structure on the upper side of the membrane layer. After forming a cantilever structure on the membrane layer and etching the membrane layer, a cantilever structure is produced in a floating state over the cavity. Also, at least one inlet hole and outlet hole can be formed in the porous layer and the membrane, thereby providing a sealed fluidic channel.

Claims (21)

1. A method of manufacturing a MEMS structure which comprises

forming a trench in a P-type silicon substrate;

forming an oxide film on the substrate including a barrier by embedding the trench with the oxide film;

removing the oxide film formed on the substrate, except for the barrier embedded in the trench;

forming a mask layer on the substrate where the oxide film has been removed and removing a portion corresponding to an inside of the barrier;

forming a porous layer having a predetermined thickness on the upper side of the substrate corresponding to the inside of the barrier;

etching the substrate below the porous layer to form a cavity;

removing the mask layer formed outside the barrier;

sealing the upper side of the cavity with a membrane layer; and

forming a resonator structure on the upper side of the membrane layer.

2. The method of claim 1 , which comprises forming the trench by deep reactive ion etching.

3. The method of claim 1 , which comprises forming the oxide film by thermal oxidation of the silicon substrate or by thin film deposition on the silicon substrate.

4. The method of claim 1 , which comprises removing the oxide film by chemical mechanical polishing.

5. The method of claim 1 , wherein the mask layer is formed of a silicon nitride film, deposited by chemical vapor deposition, and said etching comprises reactive ion etching.

6. The method of claim 1 , which comprises forming the porous layer by immersing the P-type silicon substrate into a chemical solution to treat it electrochemically, and applying an electric current smaller than a critical current value.

7. The method of claim 1 , which comprises forming the cavity by immersing the P-type silicon substrate into a chemical solution to treat it electrochemically, and applying an electric current larger than a critical current value.

8. The method of claim 1 , wherein the membrane layer is formed of an insulating material.

9. The method of claim 8 , wherein the membrane layer is formed of a material selected from the group consisting of an oxide film, a silicon nitride film and a polysilicon film.

10. The method of claim 9 , which comprises forming the oxide film constituting the membrane layer by a thermal process or oxidation or thin film deposition, where the thin film deposition is chemical vapor deposition.

11. The method of claim 9 , which comprises forming the silicon nitride film constituting the membrane layer by thin film deposition, where the thin film deposition is chemical vapor deposition.

12. The method of claim 9 , which comprises forming the polysilicon film constituting the membrane layer by thin film deposition, where the thin film deposition is chemical vapor deposition or physical vapor deposition.

Assignments (1)
SECURITY INTEREST Recorded Apr 28, 2022
From: VIRTUIX HOLDINGS INC.; VIRTUIX INC.; VIRTUIX MANUFACTURING LIMITED
To: VENTURE LENDING & LEASING IX, INC.; WTI FUND X, INC.
Reel/Frame 059762/0505 →