Digital pulse width modulator for use in electrostatic printing mechanisms
View Patent ↗A fully digital pulse width modulator substantially doubles resolution in a laser printer by outputting data to the laser on both the rising and falling edges of the clock cycle. A counter and the clock itself are used to select input to a multiplexer, and consequently, the data output to the laser from the multiplexer. A data selector code, generated by concatenating the binary value of the counter and the inverted clock bitwise, selects which of the 16 bits representing a pixel to place onto the data line, so that all 16 bits are output to the laser serially and sequentially in eight clock cycles. By using both the rising and falling edges of a clock cycle, the clock speed of the device is effectively doubled, without increasing actual clock speed. Device resolution is improved simply and inexpensively without major modification of printed circuit boards.
1. A method comprising:
providing a data selector means comprising a plurality of data inputs and a selector input, the data selector means adapted to select one of the data inputs based on the selector input and provide an output that corresponds to the selected data input;
applying each bit of a multi-bit image signal to a corresponding data input;
generating a data selector code at each of a rising and falling edge of a clock signal;
concatenating an output of a multi-bit counter with an output of an inverter, wherein an input of the counter is coupled to the clock signal and wherein an input of the inverter is coupled to the clock signal and wherein the binary value of the counter comprises the three most significant bits of the data selector code and the value of the inverted clock signal comprises the least significant bit;
applying the data selector code to the selector input; and
coupling the output to a light-emitting element, wherein the output specifies any width of and interval between light pulses emitted by the light-emitting element.
2. The method of claim 1 , wherein the data selector means comprises a multiplexer.
3. The method of claim 1 , wherein the multi-bit image signal comprises a sixteen-bit signal.
4. The method of claim 1 , wherein the multi-bit image signal comprises a pixel of an image.
5. The method of claim 1 , wherein the light-emitting device comprises a laser.
6. The method of claim 1 , wherein the method is implemented in a circuit comprising discrete components.
7. The method of claim 1 , wherein the method is implemented in a programmable logic device.
8. An image processing system comprising:
a data selector means comprising a plurality of data inputs and a selector input, each of the data inputs coupled to a corresponding bit of a multi-bit image signal, the data selector means adapted to select one of the data inputs based on the selector input and provide an output that corresponds to the selected data input;
a data selector code generator adapted to generate a data selector code at each of a rising and falling edge of a clock signal, the data selector code coupled to the selector input, wherein the data selector code generator comprises a multi-bit counter and an inverter and wherein an input of the counter is coupled to the clock signal and an input of the inverter is coupled to the clock signal;
wherein the binary value of the counter comprises the three most significant bits of the data selector code and the value of the inverted clock signal comprises the least significant bit; and
a light-emitting element coupled to the output, wherein the output specifies any width of and interval between light pulses emitted by the light-emitting element.
9. The system of claim 8 , wherein the data selector means comprises a multiplexer.
10. The system of claim 8 , wherein the multi-bit image signal comprises a sixteen-bit signal.
11. The system of claim 8 , wherein the multi-bit image signal comprises a pixel of an image.
12. The system of claim 8 , wherein the light-emitting device comprises a laser.
13. The system of claim 8 , wherein the system is implemented in a circuit comprising discrete components.
14. The system of claim 8 , wherein the system is implemented in a programmable logic device.