Transistor and method for manufacturing thereof

1. A method for manufacturing a transistor, the method comprising:

sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate;

etching a predetermined portion of the second insulating layer;

implanting impurity ions into the semiconductor substrate;

depositing a layer of spacer material, and forming first spacers on sidewalls of the second insulating layer by etching the layer of spacer material;

removing a first portion of the first insulating layer exposed between the first spacers and under a portion of the first spacers by a wet etching process;

depositing a gate insulating layer in a region where the first portion of the first insulating layer is removed;

forming a gate conductive plug on the gate insulating layer;

etching the second insulating layer;

forming second spacers on sidewalls of the gate conductive plug having the first spacers formed thereon; and

forming a silicide layer on an upper surface of the gate conductive plug, wherein a thickness ratio between the first insulating layer and the silicide layer is in a range of 1:4 to 1:6.

2. The method according to claim 1 , further comprising, after forming the second spacers, etching a second portion of the first insulating layer on both sides of the second spacer to expose an upper surface of the semiconductor substrate.

3. The method according to claim 2 , wherein the first insulating layer under the first spacers has a thickness of 20±5 Å.

4. The method according to claim 1 , wherein the second insulating layer is formed of a material selected from the group consisting of tetra ethyl ortho silicate (TEOS), medium temperature deposition of oxide (MTO), undoped silicate glass (USG), and silane (SiH 4 )-rich oxide.

5. The method according to claim 1 , wherein the step of implanting the impurity ions forms halo/pocket implants.

6. The method according to claim 5 , wherein the implantation of the impurity ions uses the first insulating layer as a buffer layer.

7. The method according to claim 1 , wherein the first spacer layers comprise nitride.

8. The method according to claim 1 , wherein the gate insulating layer is deposited using a method selected from the group consisting of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

9. The method according to claim 1 , wherein the gate conductive plug comprises polysilicon.

10. The method according to claim 1 , further comprising, after depositing the gate insulating layer, removing the second insulating layer by wet etching process.

11. The method according to claim 10 , wherein the removing of the second insulating layer is performed by wet etching process using a solution of dilute hydrofluoric acid (HF(49%):H 2 O) or buffered oxide etchant (BOE, NH 4 F:HF).

12. The method according to claim 1 , wherein the second spacer is formed by depositing a nitride layer or an oxide layer and etching the nitride layer or oxide layer.

13. The method according to claim 1 , wherein the silicide is formed by reacting a silicide material selected from the group consisting of Ti, Co, and Ni, with a polysilicon layer.

14. The method according to claim 1 , wherein the silicide has a thickness of 100±20 Å.

15. A method for manufacturing a transistor, comprising:

depositing a first insulating layer and a second insulating layer on a semiconductor substrate in sequence, and forming a photoresist pattern on the second insulating layer;

etching the second insulating layer by a dry etching process using the photoresist pattern as a mask;

removing the photoresist pattern after etching the second insulating layer;

implanting first impurity ions into the semiconductor substrate;

forming first spacers on sidewalls of the second insulating layer by depositing and etching a first layer of spacer material;

removing a portion of the first insulating layer exposed between the first spacers and under a portion of the first spacers using a wet etching process;

depositing a gate insulating layer on a region where the portion of the first insulating layer is removed;

forming a gate conductive plug on the gate insulating layer;

removing the second insulating layer using a wet etching process;

implanting second impurity ions into the semiconductor substrate after removing the second insulating layer;

forming second spacers on sidewalls of the gate conductive plug having the first spacers formed thereon by depositing and etching a second layer of spacer material;

implanting third impurity ions into the semiconductor substrate; and

forming a silicide layer on an upper surface of the gate conductive plug, wherein a thickness ratio between the first insulating layer and the silicide layer is in a range of 1:4 to 1:6.