Plasma display device and method of driving the same
View Patent ↗The present invention provides a plasma display device including: a plurality of scan electrodes sequentially scanned to be impressed with a scan pulse; an address electrode that is impressed with an address pulse corresponding to the scan pulse, for selection of a display pixel; a scan driving circuit generating the scan pulse; and an address driving circuit generating the address pulse. The address pulse rises in n stages (n is an integer equal to or larger than 2), and a period in a period during which the address pulse rises from a lowest voltage to a highest voltage overlaps a scan pulse immediately prior to the scan pulse corresponding to the address pulse.
1. A plasma display device comprising:
a plurality of scan electrodes sequentially scanned to be impressed with a scan pulse;
an address electrode that is impressed with an address pulse corresponding to the scan pulse, for selection of a display pixel;
a scan driving circuit generating the scan pulse; and
an address driving circuit generating the address pulse,
wherein the address pulse falls in n stages (n is an integer equal to or larger than 2) and a period in a period during which the address pulse falls from a highest voltage to a lowest voltage overlaps a scan pulse immediately subsequent to the scan pulse corresponding to the address pulse.
2. The plasma display device according to claim 1 , wherein the period is a period during which a voltage one-stage higher than the lowest voltage is sustained.
3. The plasma display device according to claim 2 , wherein a period during which the address pulse sustains a voltage one-stage lower than the highest voltage and falls from the voltage one-stage lower than the highest voltage to the lowest voltage overlaps a scan pulse immediately subsequent to the scan pulse corresponding to the address pulse.
4. The plasma display device according to claim 1 , wherein the address pulse falls in two stages, and a voltage one-stage higher than the lowest voltage of the address pulse is substantially ½ of the highest voltage of the address pulse.
5. The plasma display device according to claim 1 , wherein the address pulse falls in two stages, and a voltage one-stage higher than the lowest voltage of the address pulse is less than ½ of the highest voltage of the address pulse.
6. The plasma display device according to claim 1 , wherein, when the address pulse falls in n stages from the highest voltage to the lowest voltage, a displacement voltage at each fall stage in the n stages is 1/n of a difference voltage between the lowest voltage and the highest voltage.
7. The plasma display device according to claim 1 , wherein a displacement voltage when the address pulse falls from a voltage one-stage higher than the lowest voltage to the lowest voltage is lower than a displacement voltage when the address pulse falls at the other stage.
8. The plasma display device according to claim 1 , wherein the address pulse rises in n stages, and a period during which the address pulse rises from the lowest voltage to a voltage one-stage lower than the highest voltage and sustains the voltage one-stage lower than the highest voltage overlaps a scan pulse corresponding to said period.