IP Library Granted Patent US 7,616,211
Granted Patent B2
US 7,616,211 · App. 11/302,534 · Granted Nov 10, 2009

Rendering processor, rasterizer and rendering method

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Quick Facts
Patent No.
US 7,616,211
App. No.
11/302,534
Granted
Nov 10, 2009
Kind
B2
Abstract

A shader sends a “completely full” signal to a buffer control unit when a head pixel in a first pass input from a DDA arrives at a final stage of a pipeline process. When the head pixel in the first pass arrives at a stage in the middle of the pipeline process, the shader sends an “almost full” signal to the buffer control unit and a primitive generating unit. Upon receiving the “almost full” signal, the primitive generating unit suspends the generation of rendering primitives in the first pass and starts generating rendering primitives in the second pass. Upon receiving the “almost full” signal, the buffer control unit supplies the rendering primitives in the first pass from the setup processing unit to the DDA via a temporary buffer. Upon receiving the “completely full” signal, the buffer control unit switches to a second pass and directly supplies the rendering primitives in the second pass from the setup processing unit to the DDA.

Claims (27)

1. A rendering processor for multipass rendering in which a rendering process on rendering primitives are divided into a plurality of operation passes, comprising:

a primitive generating unit which generates data related to the rendering primitives processed in each of the operation passes in multipass rendering;

a rasterizer which rasterizes the data related to the rendering primitives in each of the operation passes and input from the primitive generating unit so as to sequentially generate pixel data; and

a shader which processes the pixel data by executing an instruction in each of the operation passes using a pipeline process, wherein

the shader supplies a pass switching signal to the primitive generating unit with a time margin before first pixel data in a current operation pass arrives at a final stage of the pipeline process, and

the primitive generating unit is prompted by the receipt of the pass switching signal to suspend the generation of the data related to the rendering primitives in the current operation pass and starts generating the data related to the rendering primitives in a next operation pass.

2. The rendering processor according to claim 1 , wherein the time margin is set in accordance with time required between the start of generation of the rendering primitives by the primitive generating unit and the input of the rendering primitives to rasterization by the rasterizer.

3. The rendering processor according to claim 1 , wherein the rasterizer includes a digital differential analyzer for transforming the data related to the rendering primitives into the pixel data by digital differential analysis, and wherein the time margin is set in accordance with time required between the start of generation of the rendering primitives by the primitive generating unit and a point of time immediately before the rendering primitives are input to digital differential analysis by the digital differential analyzer.

4. The rendering processor according to claim 1 , wherein a number of remaining stages in the pipeline process counted from the final stage of the pixel pipeline process is determined in accordance with the time margin, and the shader supplies the pass switching signal to the primitive generating unit when the first pixel data in the current operation pass arrives at a position removed from the final stage of the pipeline process by the number of remaining stages.

5. The rendering processor according to claim 1 , wherein the shader supplies, to the rasterizer, a pixel input suspension signal for suspending the input of the pixel data in the current operation pass when the first pixel data in the current operation pass arrives at the final stage of the pipeline process, and the rasterizer is prompted by the receipt of the pixel input suspension signal to suspend rasterizing the data related to the rendering primitives being processed in the current operation pass and to switch to rasterization of the data related to the rendering primitives to be processed in the next operation pass.

6. The rendering processor according to claim 5 , wherein the rasterizer includes a temporary buffer for temporarily holding the data related to the rendering primitives input from the primitive generating unit, the shader also supplies the pass switching signal to the rasterizer, and the rasterizer rasterizes the data related to the rendering primitives in the current operation pass, buffering the data in the temporary buffer, in a period between the receipt of the pass switching signal and the receipt of the pixel input suspension signal.

7. The rendering processor according to claim 6 , wherein the rasterizer discards the data related to the rendering primitives in the current operation pass that remain in the temporary buffer when the rasterizer receives the pixel input suspension signal and rasterizes the data related to the rendering primitives in the next operation pass without buffering the data in the temporary buffer.

8. The rendering processor according to claim 7 , wherein the rasterizer informs the primitive generating unit of the number of rendering primitives in the current operation pass discarded from the temporary buffer, and the primitive generating unit goes back a number of steps commensurate with the number of discarded rendering primitives before resuming a process in the current operation pass to generate the data related to the rendering primitives and inputting the same to the rasterizer.

9. A rasterizer for rasterizing data related to rendering primitives for multipass rendering in which a rendering process on the rendering primitives are divided into a plurality of operation passes, rasterization proceeding in each of the operation passes, comprising:

a setup processing unit which sets up parameters related to digital differential analysis for the data related to the rendering primitives in each of the operation passes;

a temporary buffer which temporarily holds the data related to the rendering primitives output from the setup processing unit;

a digital differential analyzer which transforms the data related to the rendering primitives into pixel data by referring to the parameters related to digital differential analysis; and

a buffer control unit which switches between indirect supply using the temporary buffer and direct supply bypassing the temporary buffer, for supply of the data related to the rendering primitives from the setup processing unit to the digital differential analyzer.

10. The rasterizer according to claim 9 , wherein the buffer control unit suspends the supply of the data related to the rendering primitives being processed in the current operation pass to the digital differential analyzer and switches to the supply of the data related to the rendering primitives to be processed in the next operation pass to the digital differential analyzer, when the buffer control unit receives, from a shader performing a pipeline process on the pixel data generated by the rasterizer, a pixel input suspension signal for suspending the input of the pixel data in the current operation pass as a result of the first pixel data in the current operation pass arriving at a final stage of the pipeline process.

11. The rasterizer according to claim 10 , wherein, when the buffer control unit receives, from the shader performing the pipeline process on the pixel data generated by the rasterizer, a pass switching signal with a time margin before the arrival of the first pixel data in the current operation pass at the final stage of the pipeline process, the buffer control unit supplies the data related to the rendering primitives in the current operation pass to the digital differential analyzer, buffering the data in the temporary buffer, in a period of time between the receipt of the pass switching signal and the receipt of the pixel input suspension signal.

12. The rasterizer according to claim 11 , wherein the buffer control unit discards the data related to the rendering primitives in the current operation pass that remain in the temporary buffer when the buffer control unit receives the pixel input suspension signal and supplies the data related to the rendering primitives in a next operation pass to the digital differential analyzer without buffering the data in the temporary buffer.

13. A rendering method for rasterizing data related to rendering primitives for multipass rendering in which a rendering process on the rendering primitives are divided into a plurality of operation passes, rasterization proceeding in each of the operation passes, comprising:

setting up parameters related to digital differential analysis for the data related to the rendering primitives in each of the operation passes; and

pixelizing the rendering primitives by referring to the parameters related to digital differential analysis, wherein

when switching between operation passes, the data related to the rendering primitives in the current operation pass is buffered in a temporary buffer before being pixelized, the buffer data is retrieved in the FIFO order from the temporary buffer, and the retrieved data is sequentially pixelized until the parameters related to digital differential analysis for the first rendering primitive in a next operation pass has been set up, and

when not switching between operation passes, the data related to the rendering primitives in the current operation pass is pixelized while bypassing the temporary buffer.

14. The rendering method according to claim 13 , wherein, at the time of switching between operation passes, the data related to the rendering primitives in the current operation pass buffered is discarded and the data related to the rendering primitives in the next operation pass is pixelized without being buffered, when the parameters related to digital differential analysis for the data related to the first rendering primitive in the next operation pass has been set up.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2011
From: SONY NETWORK ENTERTAINMENT PLATFORM INC.
To: SONY COMPUTER ENTERTAINMENT INC.
Reel/Frame 027481/0351 →
CHANGE OF NAME Recorded Dec 26, 2011
From: SONY COMPUTER ENTERTAINMENT INC.
To: SONY NETWORK ENTERTAINMENT PLATFORM INC.
Reel/Frame 027445/0657 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2006
From: NAOI, JUNICHI
To: SONY COMPUTER ENTERTAINMENT INC.
Reel/Frame 017274/0082 →