Device having a low-voltage trigger element
View Patent ↗An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues.
1. An electronic device comprising:
a triggerable device having at least a first circuit element in a first voltage domain, wherein said triggerable device is coupled from a first pad to a first potential in the first voltage domain;
a trigger device, having at least a second circuit element only of a second voltage domain, coupled to the triggerable device to provide trigger current to turn on the triggerable device, wherein the second voltage domain has a supply voltage lower than the supply voltage of the first voltage domain and said second circuit element is a low voltage element in a low voltage well area, the low voltage well area is a P+/LV-Nwell.
2. The device of claim 1 wherein the triggerable device is an ESD device.
3. The device of claim 1 wherein the triggerable device is a MOS driver.
4. The device of claim 1 wherein the MOS driver is an NMOS transistor.
5. The device of claim 4 wherein the trigger device is an LV-PMOS transistor coupled to a gate of an HV-NMOS transistor, where the LV-PMOS transistor has a floating gate.
6. The device of claim 4 wherein the trigger device is an LV-PMOS transistor coupled to a bulk region of an HV-NMOS transistor, where the LV-PMOS transistor has a floating gate.
7. The device of claim 4 wherein the trigger device is an LV-PMOS transistor coupled to a gate of an HV-NMOS transistor, where the LV-PMOS transistor has a gate coupled to a I/I pad and having a gate oxide with a thickness similar to a thickness of the gate oxide of the HV-NMOS transistor.
8. The device of claim 5 wherein the floating gate is coupled to a gate control circuit.
9. The device of claim 8 wherein the gate control circuit comprises a diode divider.
10. The device of claim 8 wherein the gate control circuit comprises a bias control element for maintaining the trigger device in an off-state during normal operation of a circuit protected by the device.
11. The device of claim 6 wherein the floating gate is coupled to a gate control circuit.
12. The device of claim 1 wherein the gate control circuit comprises a diode divider.
13. The device of claim 11 wherein the gate control circuit comprises a bias control element for maintaining the trigger device in an off-state during normal operation of a circuit protected by the device.
14. The device of claim 1 wherein the trigger device is a diode.
15. The device of claim 1 wherein the trigger device is a bipolar transistor.
16. The device of claim 1 wherein the trigger device comprises an area without a shallow trench isolation.
17. The device of claim 16 having a silicide block.
18. The device of claim 1 wherein the trigger device comprises a sidewall junction.
19. The device of claim 1 wherein the triggerable device is an NPN bipolar device.
20. The device of claim 1 wherein the triggerable device is an SCR.
21. The device of claim 1 wherein the triggerable device is a MOS.
22. The device of claim 1 wherein the triggerable device is a bigFET.
23. The device of claim 1 wherein the triggerable device is a NMOS.
24. The device of claim 1 wherein the triggerable device is a PMOS.
25. The device of claim 1 wherein the triggerable device is a PNP bipolar device.
26. An electronic device comprising:
a triggerable device having at least a first circuit element in a first voltage domain, wherein said triggerable device is coupled from a first pad to a first potential in the first voltage domain;
a trigger device, having at least a second circuit element only of a second voltage domain, coupled to the triggerable device to provide trigger current to turn on the triggerable device, wherein the second voltage domain has a supply voltage lower than the supply voltage of the first voltage domain and said second circuit element is a low voltage element in a low voltage well area, the low voltage well area is a N+/LV-Pwell.