IP Library Granted Patent US 7,765,251
Granted Patent B2
US 7,765,251 · App. 11/303,363 · Granted Jul 27, 2010

Signal averaging circuit and method for sample averaging

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Quick Facts
Patent No.
US 7,765,251
App. No.
11/303,363
Granted
Jul 27, 2010
Kind
B2
Abstract

An averaging circuit and method are provided to compute a running average over a number of samples without the need for maintaining a large sample queue or register. Generally, the method includes the steps of (i) receiving and accumulating data samples in a plurality of sample-accumulators while counting the number of samples received in a sample-counter; (ii) alternately selecting the sum of the samples accumulated in each of the sample-accumulators; (iii) dividing the sum of the samples accumulated in a selected sample-accumulator by the number of samples received to provide an average of the samples accumulated therein; and (iv) interleaving selection of the plurality of sample-accumulators and alternating reset of each to provide a running average over a number of samples.

Claims (41)

1. A method of computing a running average of samples of data over a number of samples, the method comprising steps of:

receiving and accumulating data samples in plurality of sample-accumulators of a signal averaging circuit while counting the number of samples received in a sample counter;

alternately selecting an average of the samples accumulated in each of the plurality of sample accumulators by dividing the sum of the samples accumulated in each of the plurality of sample accumulators by the number of samples accumulated therein; and

alternately resetting each of the sample accumulators after a number (N) of samples have been received,

whereby a running average is provided over ((M−)·N) samples where M is the number of sample-accumulators.

2. A method according to claim 1 , wherein the step of alternately selecting an average of the samples accumulated in each of the plurality of sample-accumulators comprises the steps of

dividing the sum of the samples accumulated in each of the plurality of sample-accumulators by the number of samples received in each of the plurality of sample-accumulator to provide from each of the plurality of sample-accumulators an average of the samples accumulated therein; and

interleaving selection of the average of the samples accumulated from each of the plurality of sample-accumulators.

3. A method according to claim 1 , wherein the step of alternately selecting an average of the samples accumulated in each of the plurality of sample-accumulators comprises the steps of:

alternately selecting the sum of the samples accumulated in each of the plurality of sample-accumulators; and

dividing the sum of the samples accumulated in a selected sample-accumulator by the number of samples received to provide an average of the samples accumulated therein.

4. A method according to claim 3 , further comprising the step of resetting the sample-counter following N of cycles.

5. A method according to claim 4 , wherein the step of dividing the sum of the samples comprises the step of dividing the sum of the samples accumulated in a selected sample-accumulator by the sum of ((M−1)·N ) and the number of samples received after the last sample counter reset where M is number of sample-accumulators.

6. A method according to claim 5 , wherein the step of receiving and accumulating samples comprises the step of receiving and accumulating samples in a first and a second sample-accumulator.

7. A method according to claim 6 , wherein the step of interleaving selection of the average and alternating reset of each of the sample-accumulators comprises the steps of:

after N samples have been received resetting the second sample-accumulator while resetting the sample counter after the reset selecting as the running average the average of the samples accumulated in the first sample-accumulator;

after 2N samples have been received resetting the first sample-accumulator while resetting the sample-counter after the reset selecting as the running average the average of the samples accumulated in the second sample-accumulator; and

repeating the above steps.

8. A method according to claim 1 , further comprising an initial step of selecting the number (N) of samples over which the running average is to be provided.

9. A signal averaging circuit for computing a running average over a number of samples of data, the circuit comprising:

a plurality of sample-accumulators to receive and accumulate samples;

a sample-counter to count the number of samples received up to a predetermined number (N);

a selection circuit to alternately select a sum of the samples accumulated in each of the plurality of sample-accumulators;

a divider to divide the sum of the samples accumulated in the selected sample-accumulator by the sum of ((M−1)·N) and the number of samples received after the last sample counter reset to provide from the selected sample-accumulator an average of the samples accumulated therein; and

a reset circuit to alternately reset each of the sample-accumulators after N samples have been received, whereby, a running average is provided over ((M−1)·N) samples where M is number of sample accumulators.

10. A circuit according to claim 9 , wherein the reset circuit is configured to reset the sample-counter following N of cycles.

11. A circuit according to claim 10 , wherein the plurality of sample-accumulators comprises a first sample-accumulator and a second sample-accumulator.

12. A circuit according to claim 11 , wherein the selection circuit is adapted to select the sum of the samples accumulated in the first sample-accumulator to compute the running average after N samples (and subsequent odd sets of N samples) have been received, and to select the sum of the samples accumulated in the second sample-accumulator to compute the running average after 2N samples (and subsequent even sets of N samples) have been received.

13. A circuit according to claim 12 , wherein the reset circuit is adapted to reset the second sample-accumulator after N samples (and subsequent odd sets of N samples) have been received while the average of the samples accumulated in the first sample-accumulator is selected as the running average, and to reset the first sample-accumulator after 2N samples (and subsequent even sets of N samples) have been received while the average of the samples accumulated in the second sample-accumulator is selected as the running average.

14. A circuit according to claim 13 , wherein the sample-counter is a n-bit forward counter where N=2 n , and wherein the sample-counter is configured to roll over to zero after each set of N samples has been received.

15. A signal averaging circuit for computing a running average over a number of samples of data the circuit comprising:

a plurality of sample-accumulating means for receiving and accumulating digital samples of a signal;

counting means for counting the number of samples received in the plurality of sample-accumulating means;

selection means for alternately selecting from an output of each of the plurality of accumulating means a sum of the samples accumulated therein;

dividing means for dividing the sum of the samples accumulated in the selected sample-accumulating means by the number of samples received in the selected sample-accumulating means to provide average of the samples accumulated therein; and

reset means for alternately resetting the plurality of sample-accumulating means at regular intervals offset with respect to each other by N samples. whereby, a running average is provided.

16. A circuit according to claim 15 , wherein the reset means is further adapted to reset the sample counter when it reaches N.

17. A circuit according to claim 16 wherein the plurality of sample-accumulating means comprises a first sample-accumulator and a second sample-accumulator.

18. A circuit according to claim 17 , wherein the selection means is adapted to select the sum of the samples accumulated in the first sample-accumulator to compute the running average after N samples (and subsequent odd sets of N samples) have been received, and to select the sum of the samples accumulated in the second sample-accumulator to compute the running average after 2N samples (and subsequent even sets of N samples) have been received.

19. A circuit according to claim 18 , wherein the reset means is adapted to reset the second sample-accumulator after N samples (and subsequent odd sets of N samples) have been received while the average of the samples accumulated in the first sample-accumulator is selected as the running average, and to reset the first sample-accumulator after 2N samples (and subsequent even sets of N samples) have been received while the average of the samples accumulated in the second sample-accumulator is selected as the running average.

20. A circuit according to claim 19 , wherein the counting means is a n-bit forward counter where N=2n, and wherein the sample-counter is configured to roll over to zero after each set of N samples has been received.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 052487/0808 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2008
From: SILICON LIGHT MACHINES CORPORATION
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 020907/0752 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2005
From: XU, YANSUN; KRISHNAN, GOPALAKRISHNAN P.
To: SILICON LIGHT MACHINES CORPORATION
Reel/Frame 017390/0840 →