Efficient decoders for LDPC codes
View Patent ↗An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing. The decoder may also employ a novel method for generating check node to bit node messages through a prescribed series of pair-wise computations.
1. A method of iteratively decoding LDPC encoded information comprising:
processing, in an iteration of the method, a first group of check nodes in parallel, at least two of the check nodes in the first group connected to a common bit node, and thereby generating a plurality of check node to bit node messages;
updating, in the same iteration, a plurality of bit estimates, each corresponding to a bit connected to at least one check node in the first group, responsive to the plurality of check node to bit node messages, before processing a second group of check nodes in the iteration; and
processing, in the same iteration, the second group of check nodes responsive to the updated plurality of bit estimates.
2. The method of claim 1 further comprising performing the first processing step by a plurality of processors operating in parallel on different ones of the check nodes in the first group.
3. The method of claim 1 further comprising storing the updated block of bit estimates in a memory.
4. The method of claim 3 wherein the updated bit estimates are hard decision bit estimates.
5. The method of claim 3 wherein the messages are generated responsive to soft decision, extrinsic bit estimates.
6. The method of claim 4 wherein the updated bit estimates are LLR estimates.
7. The method of claim 6 further comprising storing the plurality of check node to bit node messages in a memory.
8. The method of claim 7 further comprising updating the bit estimates by adding to each estimate all check node to bit node messages in the plurality of check node to bit node messages for the bit node corresponding to the bit estimate.
9. The method of claim 7 further comprising processing both the first and second group of bit estimates responsive to extrinsic information derived from the updated plurality of bit estimates and the plurality of check node to bit node messages.
10. The method of claim 9 wherein the extrinsic information for a particular bit node to check node connection is the updated bit estimate for the bit node minus any message to that bit node generated through the processing of the check node in the previous iteration.
11. A method according to claim 1 , further including:
receiving LDPC encoded signals;
buffering the received signals in one or more buffers;
applying an LDPC decoder to iteratively decode each of the buffered signals over a number of iterations; and
terminating the iterations when an exit condition is satisfied.
12. The method of claim 11 further comprising applying the LDPC decoder to the buffered signals in accordance with a prescribed policy.
13. The method of claim 12 wherein the prescribed policy is the policy of decoding the signals in the order in which they are received.
14. The method of claim 11 wherein the exit condition is full resolution of all applicable parity check equations.
15. The method of claim 11 wherein the exit condition is successful decoding by an outer block decoder.
16. The method of claim 11 wherein the exit condition is a buffer overflow condition.
17. The method of claim 11 further comprising dynamically changing the number of iterations applied from signal to signal.
18. The method of claim 11 wherein a signal is received over a reception time, and may be decoded over a decoding time that exceeds the signal reception time.