IP Library Granted Patent US 7,538,399
Granted Patent B2
US 7,538,399 · App. 11/303,653 · Granted May 26, 2009

Thin film transistor substrate and manufacturing method thereof

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Quick Facts
Patent No.
US 7,538,399
App. No.
11/303,653
Granted
May 26, 2009
Kind
B2
Abstract

The present invention relates to a thin film transistor (TFT) substrate and method of making such a TFT substrate. The structure of the TFT substrate helps prevent damage to signal lines in non-display areas.

Claims (42)

1. A thin film transistor substrate comprising:

dummy gate pads parallel to each other formed on a non-display area of an insulating substrate;

a gate-insulating layer formed on the dummy gate pads;

a data wiring comprising a data line provided between the dummy gate pads;

a data-insulating layer formed on the data wiring line;

an organic layer formed on the data-insulating layer and having a contact hole exposing the data pad; and

a contact subsidiary part covering the data pad exposed through the contact hole.

2. The thin film transistor substrate according to claim 1 , wherein the gate-insulating layer and the data-insulating layer are a SiNx.

3. The thin film transistor substrate according to claim 1 , wherein a thickness of the organic layer formed on the dummy gate pads is less than a thickness of the organic layer formed in a display area.

4. A method of making a thin film transistor substrate, comprising:

forming a shorting bar in a pad area on an insulting substrate;

forming a gate-insulating layer on the shorting bar;

forming a data line crossing the shorting bar on the gate-insulating layer; and

forming a data-insulating layer and an organic layer on the data line, wherein a thickness of the organic layer situated on the shorting bar is thicker than a thickness of the organic layer situated on a portion of the pad area except where the shorting bar is formed.

5. The method according to claim 4 , further comprising:

forming a contact hole to expose the shorting bar and the data line by etching the gate-insulating layer and the data-insulating layer using the organic layer as a mask; and

forming a bridge part that connects the shorting bar to the data line by depositing and patterning a transparent conductive layer.

6. The method according to claim 4 , further comprising removing a portion of the organic layer formed in a region where the shorting bar is formed by grinding the organic layer in the region where the shorting bar is formed.

7. The method according to claim 4 , wherein the organic layer that is to be formed in a region where the shorting bar is formed is patterned by a mask having a slit, and the organic layer that is to be formed in a region of the pad area where the shorting bar is not formed is patterned by a mask that does not has a slit, when the organic layer is formed.

8. The method according to claim 5 , wherein said forming the organic layer comprises:

forming a bridge organic layer hole in a predetermined region of the shorting bar or the data line; and

forming a slit pattern around the bridge organic layer hole, wherein said forming of the contact hole comprises etching the gate-insulating layer and the data-insulating layer by using the slit pattern formed around the bridge organic layer hole as a mask.

9. The method according to claim 8 , wherein the slit pattern is formed to surround the bridge organic layer hole.

10. The method according to claim 8 , further comprising removing a portion of the organic layer formed in a region where the shorting bar is formed by grinding the organic layer in the region where the shorting bar is formed.

11. The method according to claim 8 , wherein the organic layer that is to be formed in a region where the shorting bar is formed is patterned by a mask having a slit, and the organic layer that is to be formed in a region of the pad area where the shorting bar is not formed is patterned by a mask that does not has a slit, when the organic layer is formed.

12. The method according to claim 10 , wherein the organic layer that is to be formed in the region where the shorting bar is formed is patterned by a mask having a slit, and the organic layer that is to be formed in a region of the pad area where the shorting bar is not formed is patterned by a mask that does not has a slit, when the organic layer is formed.

13. The method according to claim 6 , wherein the organic layer that is to be formed in a region where the shorting bar is formed is patterned by a mask having a slit, and the organic layer that is to be formed in a region of the pad area where the shorting bar is not formed is patterned by a mask that does not has a slit, when the organic layer is formed.

14. A method of making a thin film transistor substrate, comprising:

forming a shorting bar in a pad area on an insulting substrate;

forming a insulating layer on the shorting bar;

forming a signal line crossing the shorting bar on the insulating layer;

forming an organic layer on the signal line;

forming a contact hole to expose the shorting bar and the signal line by etching the insulating layer and the data-insulating layer using the organic layer as a mask; and

forming a bridge part that connects the shorting bar to the signal line by depositing and patterning a transparent conductive layer.

15. The method according to claim 14 , wherein a thickness of the organic layer situated on the shorting bar is thicker than a thickness of the organic layer situated on a portion of the pad area except where the shorting bar is formed.

16. The method according to claim 14 , wherein said forming the organic layer comprises:

forming a bridge organic layer hole in a predetermined region of the shorting bar; and

forming a slit pattern surrounding the bridge organic layer hole.

17. The method according to claim 14 , further comprising removing a portion of the organic layer formed in a region where the shorting bar is formed by grinding the organic layer in the region where the shorting bar is formed.

18. The method according to claim 14 , wherein the organic layer that is to be formed in a region where the shorting bar is formed is patterned by a mask having a slit, and the organic layer that is to be formed in a region of the pad area where the shorting bar is not formed is patterned by a mask that does not has a slit, when the organic layer is formed.

19. The method according to claim 16 , wherein said forming the contact hole comprises etching the insulating layer by using the slit pattern as a mask.

20. The method according to claim 17 , wherein the organic layer that is to be formed in the region where the shorting bar is formed is patterned by a mask having a slit, and the organic layer that is to be formed in a region of the pad area where the shorting bar is not formed is patterned by a mask that does not has a slit, when the organic layer is formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029008/0145 →