Multi-channel LDPC decoder architecture
View Patent ↗A multi-channel decoder system has a decoder core at least a portion of which is configurable as a LDPC decoder that, during decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group, thus improving decoding throughput.
1. A multi-channel decoder system comprising:
a decoder core at least a portion of which comprises as a Low Density Parity Check (LDPC) decoder that, during iterative decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group;
a plurality of independent channels for sharing the decoder core by carrying data to and from the decoder core, each channel configured for carrying data from a decoder input to the decoder core, and for carrying, after at least some decoding thereof by the decoder core, the resultant decoded data from the decoder core to an output of the decoder; and
control logic for controlling application of the decoder core to data carried by the channels.
2. The multi-channel decoder system of claim 1 wherein data is received by each of the channels in a particular order, and the control logic is configured to apply the decoder core to the data carried by each of the channels in the order in which the data is received.
3. The multi-channel decoder system of claim 1 wherein the plurality of channels are physically realized as a plurality of parallel signal paths, each coupled to a separate input of the decoder system.
4. The multi-channel decoder of claim 3 wherein each of the plurality of parallel signals paths is coupled to a separate output of the decoder system.
5. The multi-channel decoder system of claim 1 wherein the at least a portion of the decoder core comprises or in configurable as a hybrid LDPC.
6. The multi-channel decoder system of claim 1 wherein the decoder core comprises or is configurable as a concatenated decoder having an inner decoder and an outer decoder, with an LDPC decoder forming the inner decoder.
7. The multi-channel decoder system of claim 1 implemented on a single integrated circuit chip.
8. The multi-channel decoder system of claim 1 , where the at least a portion of the decoder core is configurable as a Low Density Parity Check (LDPC) decoder that divides check nodes of a node representation of a LDPC code into groups, and iteratively processes the groups while processing in parallel the check nodes in a group.
9. A multi-channel decoder system comprising:
a decoder core configurable into any of a plurality of possible modes responsive to a mode signal, wherein, in one of the modes, at least a portion of the decoder core is configurable as a LDPC decoder that, during iterative decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group;
a plurality of independent channels for sharing the decoder core by carrying data to and from the decoder core, each channel configured for carrying data from a decoder input to the decoder core, and for carrying, after at least some decoding thereof by the decoder core, the resultant decoded data from the decoder core to an output of the decoder; and
control logic for controlling application of the decoder core to data carried by the channels.
10. The system of claim 9 wherein, in one mode, the decoder core forms a concatenated decoder having an inner decoder and an outer decoder, with an LDPC decoder forming the inner decoder, and a block decoder forming the outer decoder.
11. The system of claim 10 wherein, in the one mode, a Bose, Chaudhuri and Hocquenghem (BCH) decoder forms the outer decoder.
12. The system of claim 9 wherein, in a second mode, the decoder core forms a concatenated decoder having an inner decoder and an outer decoder, neither of which is configured as an LDPC decoder.
13. The system of claim 12 wherein, in the second mode, a Convolutional Code (CC) decoder forms the inner decoder.
14. The system of claim 13 wherein the CC decoder is a Viterbi decoder.
15. The system of claim 12 wherein, in the second mode, a RS decoder forms the outer decoder.
16. The system of claim 9 wherein the plurality of channels are physically realized as a plurality of parallel signal paths, each coupled to a separate input of the system.
17. The system of claim 16 wherein each of the plurality of parallel signal paths is coupled to a separate output of the system.
18. The system of claim 9 further comprising a demodulator coupled to each of the inputs of the system.
19. The system of claim 18 wherein each of the demodulators are independent.
20. The system of claim 18 wherein one or more of the demodulators is configurable in responsive to mode signal.
21. The system of claim 9 implemented on a single integrated circuit chip.