Multi-stage inverse toggle

1. An inverse toggle circuit, comprising:

a pair of input connections for receiving each of four possible input signal combinations in a fixed sequence and in a rotational manner;

four data paths defined to be exercised in accordance with a respective one of the four possible input signal combinations to be received at the pair of input connections such that each data path is to be exercised in a fixed sequence and in a rotational manner;

a first output connection defined to be controlled by a first data path and a third data path to be exercised in the fixed sequence; and

a second output connection defined to be controlled by a second data path and a fourth data path to be exercised in the fixed sequence,

wherein each data path is defined such that a currently exercised data path generates an output signal having an asserted state on the output connection defined to be controlled by the currently exercised data path, and the currently exercised data path causes a next data path in the fixed sequence to generate an output signal having a non-asserted state on the output connection defined to be controlled by the next data path in the fixed sequence.

2. An inverse toggle circuit as recited in claim 1 , wherein the fixed sequence is defined so that the first data path is to be exercised, followed by the second data path, followed by the third data path, followed by the fourth data path, then repeating with the first data path.

3. An inverse toggle circuit as recited in claim 1 , wherein each data path includes decode logic defined to detect receipt of the input signal combination that causes the data path to be exercised, the decode logic defined to generate a first signal indicating receipt of the input signal combination that causes the data path to be exercised.

4. An inverse toggle circuit as recited in claim 3 , wherein the currently exercised data path is defined to reset the first signal in the previously exercised data path.

5. An inverse toggle circuit as recited in claim 3 , wherein each data path includes amplification logic defined to generate a second signal in response to the first signal, the second signal representing an inverted version of the first signal.

6. An inverse toggle circuit as recited in claim 5 , wherein the currently exercised data path is defined to reset the second signal in the previously exercised data path.

7. An inverse toggle circuit as recited in claim 5 , wherein each data path includes signal generation logic defined to generate a pair of control signals in response to the second signal, the pair of control signals defined to direct generation of the output signal having an asserted state on the output connection defined to be controlled by the data path.

8. An inverse toggle circuit as recited in claim 7 , wherein the currently exercised data path is defined to reset a first control signal of the pair of control signals in the previously exercised data path, and the currently exercised data path is defined to reset a second control signal of the pair of control signals in the next data path in the fixed sequence.

9. An inverse toggle circuit, comprising:

a first data path defined to drive an assertion signal on a first output connection upon detection of an input state uniquely associated with the first data path;

a second data path defined to drive an assertion signal on a second output connection upon detection of an input state uniquely associated with the second data path;

a third data path defined to drive an assertion signal on the first output connection upon detection of an input state uniquely associated with the third data path; and

a fourth data path defined to drive an assertion signal on the second output connection upon detection of an input state uniquely associated with the fourth data path,

wherein the first data path is further defined to cause the second data path to drive a non-assertion signal on the second output connection upon detection of the input state uniquely associated with the first data path,

wherein the second data path is further defined to cause the third data path to drive a non-assertion signal on the first output connection upon detection of the input state uniquely associated with the second data path,

wherein the third data path is further defined to cause the fourth data path to drive a non-assertion signal on the second output connection upon detection of the input state uniquely associated with the third data path, and

wherein the fourth data path is further defined to cause the first data path to drive a non-assertion signal on the first output connection upon detection of the input state uniquely associated with the fourth data path.

10. An inverse toggle circuit as recited in claim 9 , wherein the inverse toggle circuit is defined to spread an electrical effort of each data path over multiple stages to reduce an RC time constant associated with nodes within each data path.

11. An inverse toggle circuit as recited in claim 9 , wherein the inverse toggle circuit is defined to receive a sequence of input states defined as the input state uniquely associated with the first data path, followed by the input state uniquely associated with the second data path, followed by the input state uniquely associated with the third data path, followed by the input state uniquely associated with the fourth data path, followed by repetition of the sequence with the input state uniquely associated with the first data path.

12. An inverse toggle circuit as recited in claim 9 , wherein each data path includes decode logic defined to detect receipt of the input state uniquely associated with the data path, the decode logic defined to generate a first signal within the data path, wherein the first signal indicates receipt of the input state uniquely associated with the data path.

13. An inverse toggle circuit as recited in claim 12 , wherein the first signal within the first data path is transmitted to reset the first signal within the fourth data path, the first signal within the second data path is transmitted to reset the first signal within the first data path, the first signal within the third data path is transmitted to reset the first signal within the second data path, and the first signal within the fourth data path is transmitted to reset the first signal within the third data path.

14. An inverse toggle circuit as recited in claim 12 , wherein each data path includes amplification logic defined to generate a second signal within the data path in response to the first signal within the data path, the second signal representing an inverted version of the first signal.

15. An inverse toggle circuit as recited in claim 14 , wherein the second signal within the first data path is transmitted to reset the second signal within the fourth data path, the second signal within the second data path is transmitted to reset the second signal within the first data path, the second signal within the third data path is transmitted to reset the second signal within the second data path, and the second signal within the fourth data path is transmitted to reset the second signal within the third data path.

16. An inverse toggle circuit as recited in claim 14 , wherein each data path includes signal generation logic defined to generate a pair of control signals within the data path in response to the second signal within the data path, the pair of control signals defined to direct driving of the assertion signal on the output connection associated with the data path.

17. An inverse toggle circuit as recited in claim 16 , wherein a first control signal of the pair of control signals within the first data path is transmitted to reset a first control signal of the pair of control signals within the fourth data path and is transmitted to reset a second control signal of the pair of control signals within the second data path,

wherein a first control signal of the pair of control signals within the second data path is transmitted to reset the first control signal of the pair of control signals within the first data path and is transmitted to reset a second control signal of the pair of control signals within the third data path,

wherein a first control signal of the pair of control signals within the third data path is transmitted to reset the first control signal of the pair of control signals within the second data path and is transmitted to reset a second control signal of the pair of control signals within the fourth data path, and

wherein the first control signal of the pair of control signals within the fourth data path is transmitted to reset the first control signal of the pair of control signals within the third data path and is transmitted to reset a second control signal of the pair of control signals within the first data path.

18. A method for implementing an inverse toggle function, comprising:

detecting a currently asserted input state provided to the inverse toggle gate; and

generating a pair of complementary inverse toggle output signals in response to detection of the currently asserted input state, wherein the generating causes each of the inverse toggle output signals to represent a changed state,

wherein the generating in response to the detecting is accomplished by spreading an electrical effort of the inverse toggle gate over multiple stages to reduce a logical complexity in the multiple stages, wherein the reduced logical complexity enables a reduction in RC time constant on nodes within the multiple stages.

19. A method for implementing an inverse toggle function as recited in claim 18 , wherein the currently asserted input state is one of four detectable input states asserted in a sequential rotational manner.

20. A method for implementing an inverse toggle function as recited in claim 18 , wherein the reduction in RC time constant on nodes within the multiple stages enables the nodes to be exercised at an increased rate.