Reliability clock domain crossing
View Patent ↗A data communications system is disclosed. The data communications system comprises two clock domains. A first clock domain includes a transmitter and a first clock signal. A second clock domain includes a receiver and a second clock signal. The transmitter conveys the first clock signal and a data signal to the receiver. The receiver: (a) counts a first number of transitions of the second clock signal in response to detecting a transition of the first clock signal; (b) maintains a first count of the number of transitions of the second clock signal; (c) samples the data signal and maintains a second count of the number of transitions of the second clock signal in response to detecting the first count equals a first pre-determined value; and (d) samples the data signal and resets the second count in response to detecting the second count equals a second pre-determined value.
1. A data communications system comprising:
a first clock domain including a transmitter and a first clock signal; and
a second clock domain including a receiver and a second clock signal;
wherein the transmitter is configured to convey the first clock signal and a data signal to the receiver;
wherein the receiver is configured to:
(a) count a first number of transitions of the second clock signal in response to detecting a transition of the first clock signal;
(b) maintain a first count of the number of transitions of the second clock signal;
(c) sample the data signal and maintain a second count of the number of transitions of the second clock signal in response to detecting the first count equals a first pre-determined value;
(d) sample the data signal and reset the second count in response to detecting the second count equals a second pre-determined value.
2. The system of claim 1 , wherein the receiver is further configured to repeat step (d) until the receiver receives a reset command.
3. The system of claim 1 , wherein the first pre-determined value is an integer greater than two and less than the second pre-determined value minus two.
4. The system of claim 1 , wherein the data signal comprises a series of multi-bit, parallel data samples.
5. The system of claim 4 ,
wherein to sample the data signal, the receiver is configured to load a sample of the data signal into a shift register; and
wherein the receiver is further configured to shift a bit from the shift register at the timing of each of a rising edge transition and a falling edge transition of the second clock signal.
6. A system comprising a plurality of memory banks interconnected via a serial ring bus, wherein each memory bank includes a data communications system comprising:
a first clock domain including a transmitter and a first clock signal; and
a second clock domain including a receiver and a second clock signal;
wherein the transmitter is configured to convey the first clock signal and a data signal to the receiver;
wherein the receiver is configured to:
(a) count a first number of transitions of the second clock signal in response to detecting a transition of the first clock signal;
(b) maintain a first count of the number of transitions of the second clock signal;
(c) sample the data signal and maintain a second count of the number of transitions of the second clock signal in response to detecting the first count equals a first pre-determined value;
(d) sample the data signal and reset the second count in response to detecting the second count equals a second pre-determined value;
wherein the data signal comprises a series of multi-bit, parallel data samples;
wherein to sample the data signal, the receiver is configured to load a sample of the data signal into a shift register; and
wherein the receiver is further configured to shift a bit from the shift register onto the serial ring bus at the timing of each of a rising edge transition and a falling edge transition of the second clock signal.
7. The system of claim 6 , wherein each memory bank comprises one of:
a fully buffered dual inline memory module (FB-DMM);
a synchronous dynamic random access memory (SDRAM); and
a double data rate dynamic random access memory (DDR DRAM).
8. The system of claim 6 , wherein the serial ring bus comprises a plurality of serial links, each serial link comprising one of:
a PCI Express bus;
a HyperTransport bus; and
a RapidIO interconnect.
9. A method of transmitting data from a first clock domain to a second clock domain, the method comprising:
conveying a first clock signal from the first clock domain to the second clock domain;
conveying a data signal from the first clock domain to the second clock domain;
in the second clock domain:
(a) counting a first number of transitions of a second clock signal in response to detecting a transition of the first clock signal;
(b) maintaining a first count of the number of transitions of the second clock signal;
(c) sampling the data signal and maintaining a second count of the number of transitions of the second clock signal in response to detecting the first count equals a first predetermined value:
(d) sampling the data signal and resetting the second count in response to detecting the second count equals a second pre-determined value.
10. The method of claim 9 , further comprising repeating step (d) until a reset command is received in the second clock domain.
11. The method of claim 9 , wherein the first pre-determined value is an integer greater than two and less than the second pre-determined value minus two.
12. The method of claim 9 , wherein the data signal comprises a series of multi-bit, parallel data samples.
13. The method of claim 12 , wherein sampling the data signal comprises loading a sample of the data signal into a shift register, the method further comprising shifting a bit from the shift register at the timing of each of a rising edge transition and a falling edge transition of the second clock signal.
14. The method of claim 13 , wherein the shift register is further configured to shift data onto a serial ring bus interconnecting a plurality of memory banks, wherein each memory bank comprises a fully buffered dual inline memory module (FB-DIMM).
15. A data receiver operable to receive a first clock signal and data signal, the data receiver comprising a second clock signal and configured to:
(a) count a first number of transitions of the second clock signal in response to detecting a transition of the first clock signal;
(b) maintain a first count of the number of transitions of the second clock signal;
(c) sample the data signal and maintain a second count of the number of transitions of the second clock signal in response to detecting the first count equals a first pre-determined value;
(d) sample the data signal and reset the second count in response to detecting the second count equals a second pre-determined value.
16. The data receiver of claim 15 , wherein the receiver is further configured to repeat step (d) until the receiver receives a reset command.
17. The data receiver of claim 15 , wherein the first pre-determined value is an integer greater than two and less than the second pre-determined value minus two.
18. The data receiver of claim 15 , wherein the data signal comprises a series of multi-bit, parallel data samples.
19. The data receiver of claim 18 ,
wherein to sample the data signal, the receiver is configured to load a sample of the data signal into a shift register; and
wherein the receiver is further configured to shift a bit from the shift register at the timing of each of a rising edge transition and a falling edge transition of the second clock signal.
20. The data receiver of claim 19 , wherein the shift register is further configured to shift data onto a serial ring bus interconnecting a plurality of memory banks, wherein each memory bank comprises a fully buffered dual inline memory module (FB-DIMM).