Method of correcting the phase difference between two input signals of a phase-locked loop and associated device
View Patent ↗A method for correcting the phase difference between two input signals of a phase-locked loop may include a charge pump connected to a filter. Prior to the occurrence of the first of the two input signals, a calibration phase may be carried out in which the input of the filter is disconnected from the output of the charge pump, the output voltage from the charge pump is equalized, to within a given error, with the input voltage of the filter, the amplitudes of the opposing currents flowing in the charge pump being equalized. Then, during the two respective occurrences of the two input signals, the input of the filter is reconnected to the output of the charge pump, and two phase-shifted signals that are delayed with respect to the input signals are respectively generated, in response to which the two opposing currents are, respectively and successively, interrupted, before the calibration phase is recommenced.
1. A phase-locked loop device comprising:
two inputs for receiving two input signals;
a charge pump having two opposing currents flowing therein, said charge pump connected between said two inputs;
a filter;
a calibrator, activated by an activation signal and deactivated by a deactivation signal, for equalizing an output voltage of the charge pump with an input voltage of the filter and amplitudes of the two opposing currents flowing in the charge pump; and
a controller comprising
a delay cell for delivering two delayed signals based upon the two input signals,
a control circuit for delivering, respectively and successively, and in the presence of the two delayed signals, two interruption signals to the charge pump to cause respective, successive interruptions of the two opposing currents, and
an activation/deactivation unit for delivering the activation signal prior to each occurrence of a first one of the two input signals, and the deactivation signal following the interruptions.
2. The phase-locked loop device according to claim 1 wherein the calibrator comprises an amplifier having positive and negative inputs respectively connected to an output node of the charge pump, and to an input of the filter, and a first switch controlled by the activation signal.
3. The phase-locked loop device according to claim 2 wherein the calibrator further comprises a negative current source, a second switch controlled by the deactivation signal and a third switch controlled by one of the interruption signals, the second and third switches for connecting and disconnecting an output of the amplifier to and from a control input of the negative current source.
4. The phase-locked loop device according to claim 3 wherein the activation/deactivation unit is connected to an input of the charge pump and comprises a first phase/frequency discriminator and an edge control module for delivering the activation signal and deactivation signal.
5. The phase-locked loop device according to claim 4 further comprising a control unit connected to the input of the charge pump and including a second phase/frequency discriminator connected to an output of the delay cell.
6. The phase-locked loop device according to claim 5 wherein the charge pump comprises a first transistor configured as a current source delivering a first current and connected between a power supply voltage and an output of the charge pump; and further comprising a fourth switch, a fifth switch, and a controllable current source; and wherein a control input of the first transistor is connected via the fourth switch to the power supply voltage and via a fifth switch to the controllable current source, the fourth and fifth switches controlled by one of the interruption signals.
7. The phase-locked loop device according to claim 6 further comprising a sixth switch; and wherein the charge pump further comprises a second transistor configured as a current source, delivering a second current and connected between the output of the charge pump and a reference voltage, a control input connected to the reference voltage via the sixth switch controlled by the other interruption signal.
8. The phase-locked loop device according to claim 1 wherein the delay cell comprises two modules for generating two different delays for each of the input signals.
9. The phase-locked loop device according to claim 1 wherein the delay cell comprises two modules for generating delays of each of the input signals, one of the delays being fixed and the other being adjustable.
10. The phase-locked loop device according to claim 6 wherein the first transistor comprises a PMOS transistor.
11. The phase-locked loop device according to claim 7 wherein second transistor comprises an NMOS transistor.
12. A phase-locked loop device comprising:
two inputs for receiving two input signals;
a charge pump having two opposing currents flowing therein, said charge pump connected between said two inputs;
a filter;
a calibrator, activated by an activation signal and deactivated by a deactivation signal, the calibrator for equalizing an output voltage of the charge pump with an input voltage of the filter and amplitudes of the two opposing currents flowing in the charge pump;
said calibrator comprising
an amplifier having positive and negative inputs are respectively connected to an output node of the charge pump, to an input of the filter, and a first switch controlled by the activation signal; and
a controller comprising
a delay cell having two distinct modules for generating two different delays for each of the input signals, and for delivering two delayed signals based upon the two input signals,
a control circuit for delivering, respectively and successively, and in the presence of the two delayed signals, two interruption signals to the charge pump to cause respective, successive interruptions of the two opposing currents, and
an activation/deactivation unit for delivering the activation signal prior to each occurrence of a first of the two input signals, and the deactivation signal following the interruptions.
13. The phase-locked loop device according to claim 12 wherein the calibrator further comprises a negative current source, a second switch controlled by the deactivation signal and a third switch controlled by one of the interruption signals, the second and third switches for connecting and disconnecting an output of the amplifier to and from a control input of the negative current source.
14. The phase-locked loop device according to claim 13 wherein the activation/deactivation unit is connected to an input of the charge pump and comprises a first phase/frequency discriminator and an edge control module for delivering the activation signal and deactivation signal.
15. The phase-locked loop device according to claim 14 further comprising a control unit connected to the input of the charge pump and including a second phase/frequency discriminator connected to an output of the delay cell.
16. The phase-locked loop device according to claim 15 wherein the charge pump comprises a first transistor configured as a current source delivering a first current and connected between a power supply voltage and an output of the charge pump; and further comprising a fourth switch, a fifth switch, and a controllable current source; and wherein a control input of the first transistor is connected via the fourth switch to the power supply voltage and via a fifth switch to the controllable current source, the fourth and fifth switches controlled by one of the interruption signals.
17. The phase-locked loop device according to claim 16 further comprising a sixth switch; and wherein the charge pump further comprises a second transistor configured as a current source, delivering a second current and connected between the output of the charge pump and a reference voltage, a control input connected to the reference voltage via the sixth switch controlled by the other interruption signal.
18. A method for correcting a phase difference between a first input signal and a second input signal of a phase-locked loop including a charge pump connected to a filter, the method comprising:
carrying out a calibration phase prior to an occurrence of at least one of the first input signal and the second input signal in which an input of the filter is disconnected from an output of the charge pump, an output voltage from the charge pump is equalized with an input voltage of the filter, and amplitudes of two opposing currents flowing in the charge pump are equalized;
reconnecting the input of the filter to the output of the charge pump during two respective occurrences of the first input signal and the second input signal; and
generating a first delay signal and a second delay signal that are delayed with respect to the first input signal and the second input signal, in response to which the two opposing currents are successively interrupted, respectively, before the calibration phase is recommenced.
19. The method according to claim 18 wherein the filter disconnecting and connecting from and to the charge pump occurs gradually over a time period less than a delay of at least one of the first delay signal and the second delay signal.