Array substrate for liquid crystal display device and fabricating method of the same

1. A fabricating method of an array substrate for a liquid crystal display device, comprising:

forming a gate line, a gate pad, a gate electrode, and a data pad on a substrate through a first mask process;

forming a gate insulating layer on a substantial part of an entire surface of the substrate including the gate line, the gate pad, the gate electrode, and the data pad;

forming a data line, a source-drain pattern and an active layer on the gate insulating layer and forming a gate pad contact hole and a data pad contact hole in the gate insulating layer through a second mask process using a mask including a blocking portion, a transmitting portion, and a half transmitting portion, wherein the half transmitting portion includes a first half transmitting portion and a second half transmitting portion, the first half transmitting portion having wider slits than the second half transmitting portion, the second half transmitting portion corresponding to the gate line, the gate pad and the data pad; and

forming a pixel electrode, a gate pad terminal, a data pad terminal, a source electrode, a drain electrode, and an ohmic contact layer through a third mask process.

2. The method according to claim 1 , wherein the second mask process includes:

sequentially forming an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer and a metal layer on the gate insulating layer;

forming a photoresist layer on the metal layer;

disposing the mask over the photoresist layer;

forming a first photoresist pattern by exposing the photoresist layer to light through the mask and then developing the photoresist layer, the first photoresist pattern selectively exposing the metal layer and having a first part and a second part thinner than the first part, wherein either the transmitting portion or the blocking portion of the mask corresponds to the first part and the half transmitting portion corresponds to the second part;

selectively removing the metal layer, the impurity-doped amorphous silicon layer, the intrinsic amorphous silicon layer and the gate insulating layer using the first and second parts of the first photoresist pattern as an etching mask to thereby form the gate pad contact hole and the data pad contact hole;

removing the second part of the first photoresist pattern;

selectively removing the metal layer, the impurity-doped amorphous silicon layer and the intrinsic amorphous silicon layer using the first part of the first photoresist pattern as an etching mask to thereby form the data line, the source-drain pattern, an impurity-doped amorphous silicon pattern, and the active layer; and

removing the first part of the first photoresist pattern.

3. The method according to claim 2 , wherein the third mask process includes:

forming a transparent conductive layer on a substantial part of an entire surface of the substrate including the data line and the source-drain pattern;

forming a second photoresist pattern on the transparent conductive layer;

selectively removing the transparent conductive layer using the second photoresist pattern as an etching mask to thereby form the pixel electrode, the gate pad terminal and the data pad terminal;

selectively removing the source-drain pattern and the impurity-doped amorphous silicon pattern to thereby form the source electrode, the drain electrode and the ohmic contact layer; and

removing the second photoresist pattern.

4. The method according to claim 1 , wherein the slits of the first and second half transmitting portions have a width within a range of 0.5 μm to about 2.5 μm.

5. The method according to claim 4 , wherein the first half transmitting portion includes narrower patterns between the slits than the second half transmitting portion, the patterns of the first and second half transmitting portions have a width within a range of about 0.5 μm to about 2.5 μm.

6. The method according to claim 5 , wherein the slits of the first half transmitting portion have a width of about 1.3 μm and the slits of the second half transmitting portion have a width of about 1.2 μm.

7. The method according to claim 6 , wherein the patterns of the first half transmitting portion have a width of about 1.4 μm and the patterns of the second half transmitting portion have a width of about 1.5 μm.

8. The method according to claim 1 , wherein the pixel electrode covers and contacts the drain electrode.

9. The method according to claim 1 , wherein the data pad terminal covers and contacts the data pad and one end of the data line.

10. The method according to claim 1 , wherein the first mask process further includes forming a link portion extending from the data pad, and the second mask process further includes forming a link hole exposing the link portion, wherein the link portion overlaps the data line, and the data pad terminal contacts the data line, the data pad and the link portion.

11. The method according to claim 1 , wherein the third mask process further includes forming a transparent conductive pattern extending from the data pad terminal, wherein the transparent conductive pattern covers and contacts the data line and the source electrode.

12. The method according to claim 1 , further including forming an oxide film on an exposed surface of the active layer.

13. The method according to claim 12 , wherein the oxide film is formed through an oxygen plasma treatment method.

14. The method according to claim 1 , wherein the pixel electrode overlaps a part of the gate line to thereby form a storage capacitor.

15. The method according to claim 1 , wherein the pixel electrode, the gate pad terminal and the data pad terminal are formed of a material selected from a transparent conductive material group including indium tin oxide and indium zinc oxide.

16. The method according to claim 1 , wherein forming the data line includes forming an impurity-doped amorphous silicon pattern and an intrinsic amorphous silicon pattern having a same shape as the data line.