Flat panel display
View Patent ↗The present invention discloses an organic light emitting diode capable of obtaining proper luminance and long life cycle by controlling an amount of current flowing through an organic electroluminescent device per unit pixel. The organic light emitting diode includes a luminescent device and first and second transistors for driving the luminescent device, wherein the first and second transistors have different resistance values. The first transistor is a driving transistor for driving the luminescent device. The second transistor is a switching transistor for switching on and off the driving transistor. The driving transistor may have a higher resistance value than the switching transistor.
1. A flat panel display device, comprising:
a luminescent device;
a first transistor; and
a second transistor,
wherein the first transistor and the second transistor have different resistance values,
wherein the transistor having a higher resistance value in the first transistor and the second transistor includes high concentration source/drain regions having different sizes to have different resistance values, and a region connected to the luminescent device in the high concentration source/drain regions has a smaller size compared with the other region, and
wherein the region connected to the luminescent device in the high concentration source/drain regions of the transistor has a same width and a longer length, or a same length and a narrower width, compared with the other region.
2. The flat panel display of claim 1 , wherein the first transistor is a driving transistor for driving the luminescent device, the second transistor is a switching transistor for switching on and off the driving transistor, and the driving transistor has a higher resistance value than the switching transistor.
3. The flat panel display of claim 1 , wherein a transistor having a higher resistance value in the first transistor and the second transistor includes multiple gates, a semiconductor layer having high concentration source/drain regions, and an offset region formed on the semiconductor layer between the multiple gates.
4. The flat panel display of claim 1 , wherein a transistor having a higher resistance value in the first transistor and the second transistor includes a gate electrode, high concentration source/drain region formed on both sides of the gate electrode, and an offset region formed between the gate electrode and the drain region.
5. The flat panel display of claim 3 , wherein the offset region is a high resistance region comprised of a low concentration impurity region on which low concentration impurities having the same conductivity type as the high concentration source/drain regions are doped as a whole or partially doped, or a high resistance region comprised of and intrinsic region on which impurities are not doped.
6. The flat panel display of claim 4 , wherein the offset region is a high resistance region comprised of a low concentration impurity region on which low concentration impurities having the same conductivity type as the high concentration source/drain regions are doped as a whole or partially doped, or a high resistance region comprised of an intrinsic region on which impurities are not doped.
7. The flat panel display of claim 3 , wherein the offset region is a high resistance region having a zigzag shape.
8. The flat panel display of claim 4 , wherein the offset region is a high resistance region having a zigzag shape.
9. The flat panel display of claim 1 , wherein a transistor having a higher resistance value in the first transistor and the second transistor includes high concentration source/drain regions having different geometrical structure to have different resistance values, and a region connected to the luminescent device in the high concentration source/drain regions has a higher resistance value compared with the other region.