FED having polycrystalline silicon film emitters and method of fabricating polycrystalline silicon film emitters
An FED using polycrystalline silicon film emitters has a substrate divided into a plurality of pixel regions, a plurality of polycrystalline silicon film emitters disposed within the pixel regions of the substrate, a cathode layer disposed on the substrate, a faceplate disposed above the substrate, and an anode layer disposed between the substrate and the faceplate.
1 . A field emission display (FED) having polycrystalline silicon film emitters, comprising:
a substrate divided into a plurality of pixel regions;
a plurality of polycrystalline silicon film emitters, each polycrystalline silicon emitter being disposed within each pixel region of the substrate;
a cathode layer disposed on the substrate;
a faceplate disposed above the substrate, wherein the polycrystalline film emitters and the cathode layer disposed between the substrate and the faceplate; and
an anode layer disposed between the substrate and the faceplate.
2 . The FED of claim 1 , wherein the polycrystalline silicon film emitters are low temperature polycrystalline silicon (LTPS) emitters.
3 . The FED of claim 1 , wherein the polycrystalline silicon film emitters are disposed on the cathode layer.
4 . The FED of claim 1 , wherein the cathode layer comprises a plurality of cathodes corresponding to the polycrystalline silicon film emitters.
5 . The FED of claim 4 , wherein each polycrystalline silicon emitter is disposed on each cathode.
6 . The FED of claim 5 , wherein each polycrystalline silicon emitter and each cathode are partially overlapping.
7 . The FED of claim 4 , wherein the polycrystalline silicon film emitters and the cathodes are disposed on a same level.
8 . The FED of claim 1 , wherein the anode layer is disposed on the faceplate.
9 . The FED of claim 1 , wherein the anode layer comprises a plurality of anodes disposed on the substrate, and each anode is disposed within each pixel region.
10 . The FED of claim 9 , further comprising a plurality of phosphor patterns, and each phosphor pattern is disposed on each anode.
11 . The FED of claim 1 , further comprising a gate electrode layer insulated from the cathode layer.
12 . The FED of claim 11 , wherein the gate electrode layer is disposed between the substrate and the cathode layer.
13 . The FED of claim 111 , wherein the gate electrode layer comprises a plurality of gate electrodes, and each gate electrode is disposed between any two adjacent pixel regions.
14 . The FED of claim 13 , wherein the gate electrodes are disposed on the cathode layer.
15 . The FED of claim 14 , further comprising a plurality of focusing electrodes stacked on the gate electrodes, and each focusing electrode is insulated from each gate electrode.
16 . The FED of claim 15 , further comprising a plurality of spacers, and each spacer is sandwiched in between each focusing electrode and the faceplate.
17 . The FED of claim 13 , wherein the gate electrodes are disposed on the faceplate.
18 . The FED of claim 1 , further comprising a plurality of spacers sandwiched in between the faceplate and the substrate.
19 . The FED of claim 1 , wherein the polycrystalline silicon film emitters have a thickness substantially ranging from 20 to 500 nanometers.
20 . The FED of claim 1 , wherein the polycrystalline silicon film emitters have a grain size substantially ranging from 2000 to 5500 angstroms.
21 . An electronic apparatus, comprising:
an flat panel display as claimed in claim 1
a circuit unit coupled to the flat panel display; and
a user interface coupled to the circuit unit.