Limiter based analog demodulator

1. A limiter based analog demodulator comprising:

a power amplifier receiving a base-band signal;

a local clock operating at the base-band frequency;

a first multiplier receiving an output from the power amplifier and the local clock to provide an in phase signal;

a quadrature phase shifter receiving the local clock;

a second multiplier receiving the output from the power amplifier and an output from the quadrature phase shifter to provide a quadrature signal;

a first analog filter receiving the in phase signal;

a second analog filter receiving the quadrature signal;

a first analog to digital converter connected to the first analog filter and providing a digitized in phase signal;

a second analog to digital converter connected to the second analog filter and providing a digitized quadrature signal; and

a phase detector that detects a phase of the digitized in phase and quadrature signals,

a decimation filter receiving the digitized in phase and quadrature signals and providing input data at three times a symbol rate;

a burst detector that receives the input data;

a carrier offset block responsive to the burst detector and providing an offset angle;

a rotator responsive to the offset angle to rotate the input data; and

an equalizer receiving data from the rotator for coherent demodulation.

2. A limiter based demodulator comprising:

a power amplifier receiving a base-band signal;

a local clock operating at a base-band frequency;

a first multiplier receiving an output from the power amplifier and the local clock to provide an in phase signal;

a quadrature phase shifter receiving the local clock;

a second multiplier receiving the output from the power amplifier and an output from the quadrature phase shifter to provide a quadrature signal;

a first analog filter receiving the in phase signal;

a second analog filter receiving the quadrature signal;

a first analog to digital converter connected to the first analog filter and providing a digitized in phase signal;

a second analog to digital converter connected to the second analog filter and providing a digitized quadrature signal; and

a phase detector that receives the digitized in phase and quadrature signals and includes:

a hardware accelerator receiving the digitized in phase and quadrature signals, the hardware accelerator including:

means for filtering and decimating the digitized in phase and quadrature signals to three times symbol rate;

a Burst Sync means and a TDMA means receiving the filtered and decimated signals to generate a slot timing signal;

a storage register responsive to the slot timing signal;

a DSP processor receiving signals from the storage registers, the DSP processor including:

a Clock Recovery means for estimating a timing offset;

an Interpolator means to perform timing adjustment and 3 to 2 rate conversion based on the timing offset;

an ArcTan means to convert the in phase and quadrature signals into a phase signal;

a Carrier Recovery means to perform carrier offset adjustment of the phase signal; and

Decoder means to perform final decoding of the phase signal.

3. A limiter based analog demodulator comprising:

a power amplifier receiving a base-band signal;

a local clock operating at a base-band frequency;

a first multiplier receiving an output from the power amplifier and the local clock to provide an in phase signal;

a quadrature phase shifter receiving the local clock;

a second multiplier receiving the outout from the power amplifier and an output from the quadrature phase shifter to provide a quadrature signal;

a first analog filter receiving the in phase signal;

a second analog filter receiving the quadrature signal;

a first analog to digital converter connected to the first analog filter and providing a digitized in phase signal;

a second analog to digital converter connected to the second analog filter and providing a digitized quadrature signal; and

a phase detector that detects a phase of the digitized in phase and quadrature signals, wherein the phase detector includes:

a hardware accelerator receiving the digitized in phase and quadrature signals, the hardware accelerator including:

a decimator block that decimates the digitized in phase and quadrature signals to three times symbol rate;

a burst sync block and a time division multiple access (TDMA) block receiving the decimated signals to generate a slot timing signal; and

a storage register responsive to the slot timing signal; and

a DSP processor receiving signals from the storage register, the DSP processor including:

a clock recovery block for estimating a timing offset;

an interpolator block to perform timing adjustment and 3 to 2 rate conversion based on the timing offset;

an arctangent block to convert in phase and quadrature signals from the interpolator block into a phase signal;

a carrier recovery block that performs carrier offset adjustment of the phase signal; and

a decoder block that performs final decoding of the adjusted phase signal.

4. A phase detector including:

a hardware accelerator receiving digitized in phase and quadrature signals and including:

a decimator block that decimates the digitized in phase and quadrature signals to three times symbol rate;

a burst sync block and a time division multiple access (TDMA) block receiving the decimated signals to generate a slot timing signal; and

a storage register responsive to the slot timing signal; and

a DSP processor receiving signals from the storage register, the DSP processor including:

a clock recovery block for estimating a timing offset;

an interpolator block to perform timing adjustment and 3 to 2 rate conversion based on the timing offset;

an arctangent block to convert in phase and quadrature signals from the interpolator block into a phase signal;

a carrier recovery block that performs carrier offset adjustment of the phase signal; and

a decoder block that performs final decoding of the adjusted phase signal.