IP Library Granted Patent US 8,064,501
Granted Patent B2
US 8,064,501 · App. 11/311,703 · Granted Nov 22, 2011

Method and apparatus for generating a periodic training signal

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Quick Facts
Patent No.
US 8,064,501
App. No.
11/311,703
Granted
Nov 22, 2011
Kind
B2
Abstract

In a method for generating a periodic training signal comprising cyclically expanded training symbols for a transceiver which transmits data via a data transmission channel using a predetermined number N of modulated carrier signals an address pointer for addressing a starting address in a memory is calculated for each training symbol on the basis of cyclic expansion parameters and, starting from the calculated starting address, 2*N stored samples of a transformed training symbol are read cyclically from the memory.

Claims (36)

1. A method for generating a periodic training signal comprising cyclically expanded training symbols for a transceiver which transmits data via a data transmission channel using a predetermined number N of modulated carrier signals of a multicarrier data transmission, comprising:

(a) initializing an initial address pointer to a predetermined value, wherein the initial address pointer comprises an address in a memory;

(b) starting from the address, reading cyclically from the memory 2*N stored samples to generate a first transformed training symbol;

(c) calculating a subsequent address pointer using the initial address pointer and one or more cyclic expansion parameters, thereby defining a calculated address pointer;

(d) starting from an address associated with the subsequent address pointer, reading cyclically from the memory 2*N stored samples to generate a subsequent transformed training symbol;

(e) calculating a next calculated address pointer using an immediately previous calculated address pointer and one or more cyclic expansion parameters;

(f) starting from an address associated with the next calculated address pointer, reading cyclically from the memory 2*N stored samples to generate the next transformed training symbol; and

(g) repeating acts (e) and (f) until a predetermined number of transformed training symbols are generated.

2. The method of claim 1 , wherein said one or more cyclic expansion parameters comprise a prefix length, a suffix length, and a windowing length.

3. The method of claim 2 , wherein calculating the next calculated address pointer comprises:

AP i+1 =AP i +L CP +L CS −.β,

where AP i+1 is the next calculated address pointer,

AP i is the value of the immediately previous calculated address pointer,

L CP is the prefix length,

L CS is the suffix length, and

β is the windowing length.

4. The method of claim 1 , further comprising transforming a prescribed set of training symbols by Inverse Fourier Transformation from the frequency domain to the time domain in order to produce the 2*N samples.

5. The method of claim 4 , wherein the Inverse Fourier Transformation is an Inverse Fast Fourier Transformation.

6. The method of claim 4 , further comprising writing the samples produced by the Inverse Fourier Transformation to the memory.

7. The method of claim 1 , wherein the method is carried out in accordance with an orthogonal frequency division multiplexing (OFDM) scheme, or a quadrature amplitude modulation (QAM) scheme.

8. The method of claim 1 , wherein the periodic training symbol is produced without sudden amplitude changes therein.

9. A training signal generation apparatus within a transceiver for generating a periodic training signal that comprises cyclically expanded training symbols for the transceiver which transmits data via a data transmission channel using a predetermined number N of modulated carrier signals of a multicarrier data transmission; said training signal generator apparatus comprising:

a memory configured to store 2*N samples of a transformed training symbol; and

a control logic unit configured to calculate, for each of the training symbols, an address pointer configured to point to a starting address in the memory, wherein the address pointer is calculated based on one or more cyclic expansion parameters, and wherein the control logic unit is further configured to control a cyclical reading of the samples stored in the memory, starting from the calculated starting address to produce the periodic training signal with a signal period of 2N corresponding to individual training symbols, wherein the periodic training signal trains adaptive processing blocks at a reception end;

wherein the control unit is further configured to initially initialize the address pointer to a particular value in generating a first training symbol of the periodic training signal; and

wherein the control unit is further configured to calculate iteratively each subsequent address pointer based on one or more cyclic expansion parameters and a previous one of the calculated address pointers.

10. The apparatus of claim 9 , further comprising:

an input buffer for storing bits corresponding to a plurality of QAM symbols.

11. The apparatus of claim 10 , further comprising:

an inverse Fourier transformation (IFFT) computation unit to perform IFFT for QAM symbols in the input buffer.

12. The apparatus of claim 11 , further comprising:

an output buffer; and

a multiplexer configured to selectively couple one of the memory and the IFFT computation unit in alternate fashion to the output buffer based on whether the apparatus is operating in a training mode or a normal transmission mode, respectively.

13. The apparatus of claim 12 , wherein the control logic unit is configured to provide a control signal to the multiplexer to selectively couple one of the memory and the IFFT computation unit to the output buffer in an alternate fashion.

14. The apparatus of claim 9 , wherein the apparatus is configured to carry out an orthogonal frequency division multiplexing (OFDM) scheme, or a quadrature amplitude modulation (QAM) scheme.

15. The apparatus of claim 9 , wherein the periodic training symbol is produced without sudden amplitude changes therein.

Assignments (7)
MERGER AND CHANGE OF NAME Recorded Jan 17, 2018
From: LANTIQ DEUTSCHLAND GMBH; LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 045085/0292 →
MERGER Recorded Dec 18, 2017
From: LANTIQ DEUTSCHLAND GMBH
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 044907/0045 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 025413/0340 AND 025406/0677 Recorded Apr 17, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 035453/0712 →
GRANT OF SECURITY INTEREST IN U.S. PATENTS Recorded Nov 29, 2010
From: LANTIQ DEUTSCHLAND GMBH
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 025406/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
To: LANTIQ DEUTSCHLAND GMBH
Reel/Frame 024529/0614 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2010
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
Reel/Frame 024474/0937 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2006
From: CLAUSEN, AXEL
To: INFINEON TECHNOLOGIES AG
Reel/Frame 017224/0387 →