Tuning core voltages of processors

1. A method for tuning plural processors, comprising:

varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors;

adjusting the core voltages of the plural processors within the operating range to tune the plural processors; and

adjusting the core voltages of the plural processors to increase performance of the plural processors while the plural processors operate in cycle-by-cycle lockstep, wherein the core voltages of the plural processors are raised and lowered at predetermined increments and held at voltages for predetermined dwell times to determine if an anomaly occurs.

2. The method of claim 1 further comprising:

determining a first voltage value where the plural processors exhibit anomalies while executing instructions; and

determining a second voltage value where the plural processors exhibit failures while executing instructions.

3. The method of claim 1 further comprising:

determining low-end and high-end voltages where the plural processors exhibit anomalies; and

using the low-end and high-end voltages to calculate the operating range.

4. The method of claim 1 further comprising, adjusting the core voltages of the plural processors to be in a middle of the operating range.

5. The method of claim 1 further comprising, operating the plural processors under full load to determine the operating range.

6. The method of claim 1 further comprising, raising and lowering the core voltages of the plural processors to determine voltages where failures occur in order to calculate the operating range.

7. A computer storage medium having software programming code-for causing a computer to execute a method, comprising:

lowering a core voltage of one of two processors executing instructions in synchronization to determine a first voltage value;

raising the core voltage of the one processor to determine a second voltage value; and

using the first and second voltage values to tune the core voltage of the one processor to increase performance of the two processors, wherein the first and second voltage values are voltages where anomalies occur while the two processors are executing instructions in lockstep.

8. The computer storage medium of claim 7 further comprising:

lowering the core voltage of the one processor until a first failure occurs; and

raising the core voltage of the one processors until a second failure occurs.

9. The computer storage medium of claim 7 further comprising, repeatedly lowering and raising the core voltage of the one processor in increments to determine voltage levels for anomalies.

10. The computer storage medium of claim 7 further comprising:

determining a lowest voltage where anomalies occur for each of the two processors;

determining a highest voltage where anomalies occur for each of the two processors; and

changing the core voltages of the two processors to have a voltage between the lowest and highest voltages.

11. A computer system, comprising:

memory for storing an algorithm; and

a processor for executing the algorithm which when executed causes the processor to:

raise and lower core voltages of plural processors operating in lockstep to determine an operating range having no anomalies for each of the plural processors;

change the core voltages of the plural processors within the operating range to tune the plural processors; and

determine where the plural processors exhibit failures while executing instructions under full load.

12. The computer system of claim 11 , wherein the processor further executes the algorithm to:

find a voltage where one of the plural processors first exhibits an anomaly; and

find a voltage where the one of the plural processors first exhibits a failure.

13. The computer system of claim 11 , wherein the core voltages of the plural processors are tuned to decrease an occurrence of failures while the plural processors are operating in cycle-by-cycle lockstep.

14. The computer system of claim 11 , wherein the computer system is a server computer.

15. A computer system, comprising:

memory for storing an algorithm; and

a processor for executing the algorithm which when executed causes the processor to:

raise and lower core voltages of plural processors operating in lockstep to determine an operating range having no anomalies for each of the plural processors; and

change the core voltages of the plural processors within the operating range to tune the plural processors, wherein the operating range has a lowest voltage value where anomalies first occur and a highest voltage value where anomalies first occur.

16. The computer system of claim 15 , wherein the processor further executes the algorithm to:

find a voltage where one of the plural processors first exhibits an anomaly; and

find a voltage where the one of the plural processors first exhibits a failure.

17. The computer system of claim 15 , wherein the core voltages of the plural processors are tuned to decrease an occurrence of failures while the plural processors are operating in cycle-by-cycle lockstep.

18. The computer system of claim 15 , wherein the computer system is a server computer.

19. A computer system, comprising:

memory for storing an algorithm; and

a processor for executing the algorithm which when executed causes the processor to:

raise and lower core voltages of plural processors operating in lockstep to determine an operating range having no anomalies for each of the plural processors; and

change the core voltages of the plural processors within the operating range to tune the plural processors, wherein the core voltages of the plural processors are raised and lowered at predetermined increments and held at voltages for predetermined dwell times to determine if an anomaly occurs.

20. The computer system of claim 19 , wherein the processor further executes the algorithm to:

find a voltage where one of the plural processors first exhibits an anomaly; and

find a voltage where the one of the plural processors first exhibits a failure.

21. The computer system of claim 19 , wherein the core voltages of the plural processors are tuned to decrease an occurrence of failures while the plural processors are operating in cycle-by-cycle lockstep.

22. The computer system of claim 19 , wherein the computer system is a server computer.