Manufacturing method of thin film transistor array panel using an optical mask
View Patent ↗A method for manufacturing a thin film transistor array panel using a photo mask is provided. The photo mask includes: a transmitting area and a translucent area, wherein the translucent area includes a plurality of light blocking portions blocking light, and wherein the light blocking portions have a plurality of areas blocking different amounts of light. By using this type of photo mask, a substantially flat layer of photoresist film can be deposited even on top of an uneven surface to manufacture a thin film transistor array panel. The flat photoresist film reduces processing cost and enhances the reliability of the panel manufacturing process.
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on a substrate;
forming a first insulating layer on the gate line;
forming a semiconductor layer on the first insulating layer;
forming a data line, a drain electrode, and a storage capacitor conductor on the semiconductor layer;
depositing a second insulating layer on the data line, the drain electrode, and the storage capacitor conductor;
forming a photoresist including a first portion and a second portion to be thinner than the first portion on the second insulating layer by exposing it to light through a photo mask and developing;
etching the second and first insulating layers using the photoresist as a mask to expose portions of the drain electrode and the storage capacitor conductor and to leave a first portion of the second insulating layer under the second portion of the photoresist;
removing the second portion of the photoresist;
depositing a conductive film; and
removing the second portion of the photoresist to form a pixel electrode connected to the drain electrode and the storage capacitor conductor,
wherein the photo mask include a light blocking area, a transmitting area, and a translucent area, and
wherein the translucent area includes a plurality of light blocking portions having a plurality of areas at which amounts of light blocked are different from each other.
2. The method of claim 1 , wherein the respective light blocking portions have a stripe shape.
3. The method of claim 2 , wherein the respective areas of the light blocking portions have different vertical widths.
4. The method of claim 3 , wherein the respective light blocking portions comprise:
a first area corresponding to a portion adjacent to where a near edge of the storage capacitor conductor is not formed;
a second area corresponding to an area near the edge of the storage capacitor conductor;
a third area corresponding to a portion of the storage capacitor conductor;
a fourth area corresponding to an area near an edge of an expansion of the gate line; and
a fifth area corresponding to a portion of the expansion of the gate line.
5. The method of claim 4 , wherein the first area has the narrowest vertical width.
6. The method of claim 4 , wherein the second portion of the photoresist film is positioned near the edge of the storage capacitor conductor.
7. The method of claim 1 , wherein the photo mask varies an amount of light blocked by adjusting an interval between adjacent light blocking portions.
8. The method of claim 1 , wherein the etching of the second and first insulating layers exposes portions of the data line.
9. The method of claim 1 , wherein the etching of the second and first insulating layers exposes a portion of the gate line.
10. The method of claim 1 wherein the second portion of the photoresist is positioned near an edge of the storage capacitor conductor.
11. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on a substrate;
forming a first insulating layer on the gate line;
forming a semiconductor layer on the first insulating layer;
forming a data line, a drain electrode, and a storage capacitor conductor on the semiconductor layer;
depositing a second insulating layer on the data line, the drain electrode, and the storage capacitor conductor;
forming a photoresist including a first portion and a second portion thinner than the first portion on the second insulating layer by exposing it to light through a photo mask and developing;
etching the second and first insulating layers using the photoresist as a mask to expose portions of the drain electrode and the storage capacitor conductor and to leave a first portion of the second insulating layer under the second portion of the photoresist;
removing the second portion of the photoresist;
depositing a conductive film; and
removing the second portion of the photoresist, to form a pixel electrode connected to the drain electrode and the storage capacitor conductor,
wherein the photo mask include a light blocking area, a transmitting area, and a translucent area, and
wherein the translucent area has a plurality of light blocking portions which have a predetermined size and are arranged in a matrix.
12. The photo mask of claim 11 , wherein the light blocking portions have different sizes from each other.
13. The photo mask of claim 12 , wherein the respective light blocking portions have a circular shape.
14. The photo mask of claim 11 , wherein the light blocking portions have the same size and have different formation densities in accordance with formation position.
15. The photo mask of claim 11 , wherein the respective light blocking portions have a polygon shape.
16. The photo mask of claim 15 , wherein the respective light blocking portions have a rectangular shape.
17. The method of claim 11 , wherein the etching of the second and first insulating layers exposes portions of the data line and the drain electrode.
18. The method of claim 11 , wherein the etching of the second and first insulating layers exposes a portion of the gate line.