Semiconductor device and method of manufacturing the same
View Patent ↗An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulation layer on a semiconductor substrate; forming a plurality of gate electrodes on the gate insulation layer; forming pocket regions by a pocket ion implantation process using the gate electrode as an implantation mask; forming a capping electrode layer on the gate electrode by depositing a polysilicon layer; forming lightly doped regions by low-concentration ion implantation using the capping electrode layer as an implantation mask; forming spacer layers on the sidewall of the capping electrode layer; and forming source and drain regions by high concentration ion implantation using the spacer layers as an implantation mask. The method can suppress the occurrence of the punch-through phenomenon.
1. A method of manufacturing a semiconductor device, comprising:
forming a gate insulation layer on a semiconductor substrate;
forming a plurality of gate electrodes on the gate insulation layer;
forming pocket regions by a pocket ion implantation process using the plurality of gate electrodes as an implantation mask;
forming a capping electrode layer on the upper surface and the sidewall of the plurality of gate electrodes by depositing a polysilicon layer on the semiconductor substrate formed on the plurality of gate electrodes and removing the polysilicon layer formed between the plurality of gate electrodes;
forming lightly doped regions by low-concentration ion implantation using the capping electrode layer as an implantation mask;
forming spacer layers on the sidewall of the capping electrode layer; and
forming source and drain regions by high-concentration ion implantation using the spacer layers as an implantation mask.
2. The method of claim 1 , wherein the pocket ion implantation is performed in a direction vertical to the semiconductor substrate.
3. The method of claim 1 , wherein the capping electrode layer increases the width of each of the plurality of gate electrodes to a predetermined width.
4. The method of claim 3 , wherein the capping electrode layer is formed by depositing a polysilicon layer having a thickness of 5-20 nm.