Semiconductor device with a metal line and method of forming the same
View Patent ↗A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the lower insulation layer; sequentially forming a first oxide layer, an FSG (Fluorine-doped Silicate Glass) layer, and a second oxide layer on the lower insulation layer and the first metal line; removing the first oxide layer, the FSG layer, and the second oxide layer so as to expose the first metal line; forming an upper insulation layer on the lower insulation layer and the first metal line; forming a contact hole by etching the upper insulation layer to a degree that the first metal line is exposed; and forming a second metal line by depositing a metal material in the contact hole.
1. A method of forming a metal line in a semiconductor device, the semiconductor device being electrically connected to a lower substrate and exposed upward, the method comprising:
forming a lower insulation layer on the lower substrate;
forming a first metal line on a part of the lower insulation layer;
sequentially forming a first oxide layer, an FSG layer, and a second oxide layer on the lower insulation layer and the first metal line;
removing the first oxide layer, the FSG layer, and the second oxide layer so as to expose the first metal line, wherein the second oxide layer on the lower insulation layer and the first metal line is completely removed;
forming an upper insulation layer on the lower insulation layer and the first metal line;
forming a contact hole by etching the upper insulation layer so as to expose the first metal line; and
forming a second metal line by depositing a metal material in the contact hole.
2. The method of claim 1 , wherein forming the second oxide layer comprises forming the second oxide layer from a material including a SOG material.
3. The method of claim 1 , wherein forming the second oxide layer comprises forming the second oxide layer from a material including an O 3 -TEOS (tetra-ethyl orthosilicate) material.
4. The method of claim 1 , wherein removing the first oxide layer, the FSG layer, and the second oxide layer comprises removing with a CMP (chemical mechanical polishing) process.
5. The method of claim 1 , wherein removing the first oxide layer, the FSG layer, and the second oxide layer comprises removing with an etch-back process.
6. The method of claim 1 , wherein forming the first metal line and the second metal line comprises forming the first metal line and the second metal line to contact at a connecting region, wherein the connecting region has a smaller width than that of the first metal line.
7. A semiconductor device comprising;
a first metal line formed on a lower insulation layer and having first and second sidewalls;
a first oxide layer formed on the lower insulation layer, wherein the first oxide layer encloses the first and second sidewall and partially contacts an upper insulation layer;
an FSG layer formed between the first oxide layer and the upper insulation layer;
a contact hole formed in the upper insulation layer; and
a second metal line formed in the contact hole, and contacting the first metal line at a connecting region.
8. The semiconductor device of claim 7 , wherein the connecting region has a smaller width than a width of the first metal line.