Physically highly secure multi-chip assembly
View Patent ↗A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.
1. A method for providing a physically secure multi-chip assembly, the method comprising the steps of:
mounting a first die on a first planar surface of a substrate such that electrical contacts on a first surface of the first die are located between the first surface of the first die and the first planar surface of the substrate;
mounting a second die on the first planar surface of the substrate such that electrical contacts on a first surface of the second die are located between the first surface of the second die and the first planar surface of the substrate;
providing a first conductive pathway that is connected to at least one of the electrical contacts of the first die, at least a portion of the first conductive pathway being located within the substrate;
providing a second conductive pathway that is connected to at least one of the electrical contacts of the second die, at least a portion of the second conductive pathway being located within the substrate;
providing a plurality of electrical conductors that surround at least part of the first and second conductive pathways; and
detecting a break in continuity of one or more of the electrical conductors.
2. The method according to claim 1 , wherein the first conductive pathway extends through the substrate from the first planar surface to a second planar surface of the substrate.
3. The method according to claim 1 , wherein the step of mounting the first die comprises disposing an adhesive material between the substrate and the first die so as to permanently attach the first die to the substrate.
4. The method according to claim 1 , further comprising the step of encapsulating the first and second dies in an epoxy material.
5. The method according to claim 1 , further comprising the step of erasing at least a portion of a memory upon the detection of the break in continuity.
6. The method according to claim 1 , wherein at least a portion of the electrical conductors is located between the first planar surface and a second planar surface of the substrates.
7. The method according to claim 1 , further comprising the step of electrically coupling a chip carrier to at least one of the first conductive pathway and the second conductive pathway at a second planar surface of the substrate.