Digital background calibration for time-interlaced analog-to-digital converters
View Patent ↗The present invention provides for background calibration of a time-interleaved analog-to-digital converter (TIADC). In one embodiment, a background calibrator includes a TIADC having a parallel array of time-interleaved main signal processors, each main signal processor including an ADC connected to a corresponding output FIR filter. The background calibrator also includes an auxiliary signal processor having an ADC connected to at least one corresponding output FIR filter. Additionally, the background calibrator further includes a timing calibration circuit, wherein the timing calibration circuit is configured to select one of the main signal processors, exchange the auxiliary signal processor with the selected main signal processor in the TIADC and connect the selected main signal processor to the timing calibration circuit. In an alternative embodiment, the timing calibration circuit is further configured to reduce a timing mismatch of the selected main signal processor.
1. An apparatus, comprising:
a time-interleaved analog-to-digital converter (TIADC) including a parallel array of time-interleaved main signal processors, each main signal processor including an analog-to-digital converter (ADC) connected to a corresponding output finite impulse response (FIR) filter;
an auxiliary signal processor including an ADC connected to at least one corresponding output FIR filter;
a timing calibration circuit; and
wherein said timing calibration circuit is configured to select one of said main signal processors, exchange said auxiliary signal processor with said selected main signal processor in said TIADC, and connect said selected main signal processor to said timing calibration circuit.
2. The apparatus of claim 1 , wherein said timing calibration circuit is further configured to reduce a timing mismatch of said selected main signal processor based on interpolation quantities and timing mismatch operations defined for calibration of said auxiliary signal processor.
3. The apparatus of claim 1 , wherein said timing calibration circuit is further configured to apply an input ramp voltage and employ a first sampling clock as a reference clock during calibration of said auxiliary signal processor to provide reference samples for interpolation.
4. The apparatus of claim 1 , wherein said timing calibration circuit is further configured to provide interpolated sample values, corresponding to ideal time-interleaved sampling times, between reference samples of said auxiliary signal processor.
5. The apparatus of claim 1 , wherein said timing calibration circuit is further configured to determine timing mismatches between actual time-interleaved sampling times and corresponding ideal time-interleaved sampling times.
6. The apparatus of claim 5 , wherein said timing calibration circuit is configured to reduce said timing mismatches by modifying filter coefficients of said corresponding output FIR filters.
7. The apparatus of claim 5 , wherein said timing calibration circuit is configured to reduce said timing mismatches to a level below a preselected threshold.
8. A method for calibrating a time-interleaved analog-to-digital converter (TIADC), comprising:
selecting a main signal processor, which includes an analog-to-digital converter (ADC) connected to a corresponding output finite impulse response (FIR) filter from a parallel array of time-interleaved main signal processors in said TIADC;
exchanging an auxiliary signal processor, which includes an ADC connected to at least one corresponding output FIR filter, with said selected main signal processor; and
connecting said selected main signal processor for calibration.
9. The method of claim 8 further comprising reducing a timing mismatch of said selected main signal processor based on interpolation quantities and timing mismatch operations defined for calibration of said auxiliary signal processor.
10. The method of claim 8 further comprising applying an input ramp voltage and employing a first sampling clock as a reference clock during calibration of said auxiliary signal processor to provide reference samples for interpolation.
11. The method of claim 8 further comprising providing interpolated sample values corresponding to ideal time-interleaved sampling times between reference samples of said auxiliary signal processor.
12. The method of claim 8 further comprising determining timing mismatches between actual time-interleaved sampling times and corresponding ideal time-interleaved sampling times.
13. The method of claim 12 including reducing said timing mismatches by modifying filter coefficients of said corresponding output FIR filters.
14. The method of claim 12 including reducing said timing mismatches to a level below a preselected threshold.
15. An apparatus, comprising:
a timing calibration circuit; and
a time-interleaved analog-to-digital converter (TIADC) including a parallel array of first signal processors, each first signal processor including an analog-to-digital converter (ADC) and a corresponding finite impulse response (FIR) filter; and
wherein said timing calibration circuit is configured to apply a ramp voltage to one of said signal processors and to determine a timing mismatch of said one of said signal processors based on an output signal from said one of said signal processors in response to said applied ramp voltage.
16. The apparatus of claim 15 , wherein said timing calibration circuit is configured to individually apply said ramp voltage to each one of said signal processors.
17. The apparatus of claim 16 , wherein said timing calibration circuit is configured to determine a timing mismatch by digitally interpolating said output signal of said one of said signal processors.